DLL circuit having variable clock divider

Patent metadata

Field	Value
Publication number	US-10931289-B2
Application number	US-201916536079-A
Country	US
Kind code	B2
Filing date	Aug 8, 2019
Priority date	Oct 17, 2017
Publication date	Feb 23, 2021
Grant date	Feb 23, 2021

Abstract

Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.

First claim

The invention claimed is:

1. An apparatus, comprising:
a variable clock divider configured to generate a divided clock signal based on feedback of a delay measured as a number of clock cycles of the divided clock signal; and
a delay circuit configured to receive the divided clock signal, configured to delay the divided clock signal based on the delay and provide the divided clock signal, and further configured to provide the feedback of the delay to the variable clock divider.

2. The apparatus of claim 1 , further comprising:
a clock path including the delay circuit, the clock path configured to receive an internal clock signal,
wherein the variable clock divider is further configured to receive the internal clock signal and to divide the internal clock signal to generate the divided clock signal.

3. The apparatus of claim 2 , wherein the variable clock divider has a division ratio responsive to the number of clock cycles of the internal clock signal exhibited during the delay to the internal clock signal by the clock path.

4. The apparatus of claim 2 , wherein the variable clock divider is configured to divide the internal clock signal responsive to a first command and further configured to stop dividing the internal clock signal responsive to a second command.

5. The apparatus of claim 1 , further comprising:
an output buffer; and
a replica circuit configured to receive the delayed divided clock signal and further configured to provide output clock signal feedback,
wherein the output clock signal feedback is the delayed divided clock signal having an output timing matched with an output timing of read data output from the output buffer.

6. The apparatus of claim 5 , wherein the replica circuit has substantially a same delay as the output buffer.

7. An apparatus, comprising:
a delay circuit configured to receive a clock signal and further configured to delay the clock signal for a first period measured as a number of clock cycles of the divided clock signal; and
a clock divider circuit configured to divide the clock signal based on the first period, and further configured to provide a divided clock signal.

8. The apparatus of claim 7 , wherein the clock divider circuit comprises a logic gate circuit configured to be activated responsive to an enable signal, and
wherein the enable signal is in an enable state based on a division ratio of the clock divider circuit.

9. The apparatus of claim 8 , wherein the clock divider circuit comprises a circuit configured to receive data, the circuit comprising:
a first logic circuit configured to receive the data; and
a second logic circuit
configured to provide a first enable signal and a second enable signal that is the enable signal.

10. The apparatus of claim 9 ,
wherein the first enable signal and the second enable signal are at a same logic level responsive to a first command, and
wherein the first enable signal and the second enable signal are at different logic levels responsive to a second command.

11. The apparatus of claim 9 , wherein the first logic circuit is configured to latch the data responsive to an inversion signal of the clock signal.

12. The apparatus of claim 9 , wherein the first logic circuit is a flip flop circuit.

13. The apparatus of claim 7 , wherein the clock divider circuit is further configured to divide the dock signal based on a division ratio of the clock divider circuit.

14. An apparatus, comprising:
a clock path including a delay circuit, the dock path configured to receive a clock signal; and
a variable clock divider configured to divide the clock signal to provide a divided clock signal based, at least in part, on a delay measured as a number of clock cycles of the divided clock signal to the clock signal by the clock path,
wherein the delay circuit is configured to receive the divided clock signal from the variable clock divider, to delay the divided clock signal, and further configured to provide a delayed divided dock signal.

15. The apparatus of claim 14 , wherein the variable clock divider is configured to divide the clock signal responsive to a first command and further configured to stop dividing the clock signal responsive to a second command.

16. The apparatus of claim 14 , wherein the variable clock divider comprises;
a circuit configured to receive a data signal, the circuit comprising:
a first logic circuit configured to receive the data signal; and
a second logic circuit configured to provide a first enable signal and a second enable signal;
a first logic gate circuit coupled to the circuit, configured to receive the clock signal and the first enable signal and further configure to provide a first internal clock signal; and
a second logic gate circuit coupled to the first logic circuit, configured to receive the first internal clock signal and the second enable signal and further configure to provide a second internal clock signal.

17. The apparatus of claim 16 , wherein the second enable signal is an inversion signal of the first enable signal that is delayed by a clock signal.

18. The apparatus of claim 16 , wherein the first logic circuit is configured to latch the data signal responsive to an inversion signal of the clock signal, and
wherein the first enable signal and the latched data signal are at a same logic level responsive to the first command and the first enable signal is set to a fixed logic level responsive to the second command.

19. The apparatus of claim 16 , wherein the second logic circuit is configured to receive a control signal;
wherein the first enable signal and the second enable signal are at different logic levels responsive to the control signal at a first logic level, and
wherein the first enable signal and the second enable signal are at a same logic level responsive to the control signal at a second logic level.

20. The apparatus of claim 19 , wherein the control signal is at the first logic level responsive to a first command and the control signal is at the second logic level responsive to a second command.

Assignees

• Micron Technology Inc

Inventors

• Satoh Yasuo

Classifications

• H03K5/13 Primary

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03L7/193 Primary

  the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider · CPC title

• H03L7/0997

  Controlling the number of delay elements connected in series in the ring oscillator · CPC title

• H03K21/10

  comprising logic circuits · CPC title

• H03L7/0805

  the loop being adapted to provide an additional control signal for use outside the loop · CPC title