Forwarded clock receiver based on delay-locked loop

Patent metadata

Field	Value
Publication number	US-10141940-B2
Application number	US-201515501199-A
Country	US
Kind code	B2
Filing date	Jul 8, 2015
Priority date	Aug 4, 2014
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A delay-locked loop includes a voltage control delay line and a phase detector. The phase detector includes: a sampler unit generating multiple samples obtained by sampling a data signal in a time interval corresponding to a half of a unit interval based on a clock; a mode selection unit selecting a series of samples among the multiple samples in such a way that the mode selection unit selects the series of samples starting from an odd-numbered sample, or selects the series of samples starting from an even-numbered sample, according to a mode selection signal; and an XOR unit performing an XOR operation on the samples that are adjacent to each other and outputting an operation result, the output operation result is used for controlling the voltage-controlled delay line. The delay-locked loop can greatly reduce power consumption and an area of the voltage control delay line.

First claim

What is claimed is:

1. A delay-locked loop comprising:
a voltage-controlled delay line generating a clock signal; and
a phase detector obtaining a first sample group by sampling a data signal in at least two positions at a unit interval based on the clock signal and a second sample group by sampling the data signal in at least two positions at the unit interval based on the clock signal, wherein a difference between the positions in which the second sample group is obtained and the positions in which the first sample group is obtained is a half of the unit interval,
selecting, for a first mode, the first sample group as an edge sample of the data signal and the second sample group as a data sample of the data signal, and for a second mode, the first sample group as the data sample of the data signal and the second sample group as the edge sample of the data signal, and
controlling the voltage-controlled delay line by toggling between the first mode and the second mode.

2. A forwarded clock receiver based on a delay-locked loop, the forwarded clock receiver comprising:
the delay-locked loop of claim 1 ,
wherein a received clock signal is input to the voltage-controlled delay line.

3. The delay-locked loop of claim 1 , wherein the phase detector further performs an XOR operation on the edge sample of the data signal and the data sample of the data signal that are adjacent to each other for controlling the voltage-controlled delay line.

4. The delay-locked loop of claim 1 , wherein when a preset delay time exceeds a low limit while decreasing a delay of the voltage-controlled delay line, or when the preset delay time exceeds a high limit while increasing a delay of the voltage-controlled delay line, the phase detector toggles between the first mode and the second mode.

5. A delay-locked loop comprising:
a first voltage-controlled delay line generating a first clock signal; and
a phase detector including:
a sampler generating a series of samples by sampling a data signal at time intervals corresponding to a half of a unit interval based on the first clock signal;
a mode selector selecting every odd-numbered samples among the series of samples generated from the sampler or every even-numbered samples among the series of samples generated from the sampler, according to a mode selection signal; and
an XOR operator performing an XOR operation on samples adjacent to each other among the selected samples, and outputting an operation result for controlling the first voltage-controlled delay line.

6. The delay-locked loop of claim 5 , wherein the phase detector further includes:
a struck detector toggling the mode selection signal when a control voltage for the first voltage-controlled delay line exceeds a high limit while increasing the control voltage, or when the control voltage exceeds a low limit while decreasing the control voltage.

7. The delay-locked loop of claim 5 , further comprising:
a pair of charge pump increasing or decreasing a control voltage of the first voltage-controlled delay line by using the output result of the XOR operator; and
a loop filler filtering the control voltage.

8. The delay-locked loop of claim 5 , further comprising:
a quadrature phase clock generator generating a second clock signal that is delayed by 90 degrees from the first clock signal output from the first voltage-controlled delay line and providing the second clock signal to the sampler so as to be used for generating the samples.

9. The delay-locked loop of claim 8 , wherein the quadrature phase clock generator includes:
a second voltage-controlled delay line generating the second clock signal by delaying the first clock signal;
a voltage increasing charge pump supplying a current that increases a control voltage that controls a delay of the second voltage-controlled delay line;
a voltage decreasing charge pump supplying a current that decreases the control voltage; and
a second phase detector controlling the voltage increasing charge pump and the voltage decreasing charge pump.

10. The delay-locked loop of claim 9 , wherein the second phase detector controls the voltage decreasing charge pump by using a second division signal that is obtained by dividing the second clock signal, and controls the voltage increasing charge pump by using a signal obtained by performing an NOR operation on the second division signal and a first division signal that is obtained by dividing the first clock signal.

11. A quadrature phase clock generator, the generator comprising:
a voltage-controlled delay line generating a second clock signal that is generated by delaying an input first clock signal;
a voltage increasing charge pump supplying a current that increases a control voltage that controls a delay of the voltage-controlled delay line;
a voltage decreasing charge pump supplying a current that decreases the control voltage; and
a phase detector controlling the voltage increasing charge pump and the voltage decreasing charge pump,
wherein the phase detector controls:
the voltage decreasing charge pump by using a second division signal that is obtained by dividing the second clock signal, and
the voltage increasing charge pump by using a signal obtained by performing an NOR operation on the second division signal and a first division signal that is obtained by dividing the first clock signal.

12. The quadrature phase clock generator of claim 11 , wherein a ratio between a current supply capacity of the voltage increasing charge pump and a current supply capacity of the voltage decreasing charge pump is set to 4:5.

13. A method of operating a phase detector, wherein the phase detector is used in a delay-locked loop and includes a sampler, a mode selector and an XOR operator, the method comprising:
sampling, by the sampler, a data signal at time intervals corresponding to a half of a unit interval based on a clock signal for obtaining a series of samples;
selecting, by the mode selector, every odd-numbered samples among the series of samples obtained by the sampler, or every even-numbered samples among the series of the samples obtained by the sampler, according to a mode selection signal; and
performing, by the XOR operator, an XOR operation on adjacent samples among the samples selected by the mode selector, and outputting an operation result; and
wherein the operation result is used for controlling a voltage-controlled delay line of the delay-locked loop.

14. The method of claim 13 , wherein the mode selection signal is toggled when a control voltage for the voltage-controlled delay line exceeds a high limit while increasing the control voltage, or when the control voltage exceeds a low limit while decreasing the control voltage.

15. A delay-locked loop comprising:
a voltage-controlled delay line generating a clock signal; and
a phase detector obtaining a series of samples by sampling a data signal at time intervals corresponding to a half of a unit interval based on the clock signal,
selecting, for a first mode, every odd-numbered samples among the series of samples as an edge sample of the data signal and every even-numbered samples among the series of samples as a data sample of the data signal,
selecting, for a second mode, said every odd-numbered samples among the series of samples as the data sample of the data signal and said every even-numbered samples among the series of samples as the edge sample of the data signal, and
controlling the voltage-controlled delay line by toggling between the first mode and the second mode.

16. The delay-locked loop of claim 15 , wherein the

Assignees

• Seoul Nat Univ R&Db Foundation

Inventors

• Jeong Deogkyoon
• Bae Woorham

Classifications

• H03K19/21

  EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical · CPC title

• H03L7/081

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L7/0891 Primary

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/0816

  the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input · CPC title