Imaging system and electronic device

Patent metadata

Field	Value
Publication number	US-11956570-B2
Application number	US-202017640134-A
Country	US
Kind code	B2
Filing date	Sep 7, 2020
Priority date	Sep 20, 2019
Publication date	Apr 9, 2024
Grant date	Apr 9, 2024

Abstract

An imaging system that has an image processing function and is capable of generating an interpolation image is provided. The imaging system has an additional function such as image processing and can generate an interpolation image by using image data output from an imaging device. The imaging device can perform filter processing in parallel during a light exposure period, and thus can perform a large amount of arithmetic operation and generate a high-quality interpolation image. The number of arithmetic operations can be further increased particularly during image capturing in a dark place, which requires a long exposure time. Accordingly, the frame rate can be substantially increased, and high-quality moving image data can be generated.

First claim

The invention claimed is:

1. An imaging system comprising:
an imaging device, a first semiconductor device, a second semiconductor device, and a third semiconductor device,
wherein the imaging device is configured to obtain first data and second data in each frame period,
wherein the imaging device is configured to generate third data by filter processing of the first data and generate fourth data by filter processing of the second data,
wherein the first semiconductor device is configured to generate fifth data by arithmetic operation using third data and fourth data that are obtained in an n-th frame, where n is a natural number,
wherein the first semiconductor device is configured to generate sixth data by arithmetic operation using third data and fourth data that are obtained in an (n+1)th frame,
wherein the second semiconductor device is configured to generate an interpolation image by using the fifth data and the sixth data, and
wherein the third semiconductor device is configured to generate moving image data including first data obtained in the n-th frame, the interpolation image, and first data obtained in the (n+1)th frame in this order.

2. The imaging system according to claim 1 ,
wherein the third data is generated while the second data is obtained.

3. An electronic device comprising:
the imaging system according to claim 1 ; and
a display device.

4. An imaging system comprising:
an imaging device, a first semiconductor device, a second semiconductor device, and a third semiconductor device,
wherein the imaging device is configured to obtain first data and second data,
wherein the first image is obtained in each frame period,
wherein the imaging device is configured to generate third data by filter processing of the first data and generate fourth data by filter processing of the second data,
wherein the first semiconductor device is configured to generate fifth data by arithmetic operation using third data and fourth data that are obtained in an n-th frame, where n is a natural number,
wherein the first semiconductor device is configured to generate sixth data by arithmetic operation using third data and fourth data that are obtained in an (n+1)th frame,
wherein the second semiconductor device is configured to generate an interpolation image by using the fifth data and the sixth data, and
wherein the third semiconductor device is configured to generate moving image data including first data obtained in the n-th frame, the interpolation image, and first data obtained in the (n+1)th frame in this order.

5. The imaging system according to claim 4 ,
wherein filter processing of the first data obtained in the n-th frame is performed in the (n+1)th frame.

6. The imaging system according to claim 4 ,
wherein the imaging device comprises a pixel block, a first circuit, and a second circuit,
wherein the pixel block comprises a plurality of pixels,
wherein the first circuit is configured to supply a first potential or a second potential to each of the pixels,
wherein each of the pixels is configured to obtain the first data,
wherein each of the pixels is configured to generate the second data by adding the first potential to the first data,
wherein each of the pixels is configured to generate the third data by adding the second potential to the first data, and
wherein the second circuit is configured to generate the fourth data corresponding to a difference between a sum of the second data output from the plurality of pixels and a sum of the third data output from the plurality of pixels.

7. The imaging system according to claim 6 ,
wherein each of the pixels comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a photoelectric conversion device, and a capacitor,
wherein one electrode of the photoelectric conversion device is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor, and the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the third transistor, a gate of the fourth transistor, and one electrode of the capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor, and
wherein the other electrode of the capacitor is electrically connected to one of a source and a drain of the sixth transistor.

8. The imaging system according to claim 7 ,
wherein the first circuit is electrically connected to the other of the source and the drain of the sixth transistor.

9. The imaging system according to claim 7 ,
wherein the second circuit is configured to be a correlated double sampling circuit, and
wherein the second circuit is electrically connected to the other of the source and the drain of the fifth transistor.

10. The imaging system according to any one of claim 7 ,
wherein at least one of the first transistor to the sixth transistor comprises a metal oxide in a channel formation region, and the metal oxide comprises In, Zn, and M, where M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf.

Assignees

• Semiconductor Energy Lab

Inventors

• Negoro Yusuke
• Yoneda Seiichi

Classifications

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/80377 Primary

  characterised by the channel of the transistor, e.g. channel having a doping gradient · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10F39/12

  Image sensors · CPC title

• H04N7/0135 Primary

  involving interpolation processes (interpolation-based image scaling G06T3/4007; interpolation for video coding H04N19/587, H04N19/59) · CPC title