Imaging device comprising current mirror circuit

US10964743B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10964743-B2
Application numberUS-202016822330-A
CountryUS
Kind codeB2
Filing dateMar 18, 2020
Priority dateDec 10, 2014
Publication dateMar 30, 2021
Grant dateMar 30, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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Abstract

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A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.

First claim

Opening claim text (preview).

What is claimed is: 1. An imaging device comprising: a first pixel; a second pixel; and a current mirror circuit, wherein a first current corresponding to a current flowing through the first pixel flows to an input transistor of the current mirror circuit, wherein a second current flows to an output transistor of the current mirror circuit, and wherein a difference between the second current and a third current corresponding to a current flowing through the second pixel is calculated. 2. The imaging device according to claim 1 , wherein current value of the second current is the same as current value of the first current. 3. The imaging device according to claim 1 , wherein the current flowing through the first pixel is a current corresponding to a state in which a charge retention portion included in the first pixel is initialized. 4. An imaging device comprising: a first pixel; a second pixel; and a current mirror circuit, wherein a first current corresponding to a current flowing through the first pixel flows to an input transistor of the current mirror circuit, wherein a second current flows to an output transistor of the current mirror circuit, wherein a difference between the second current and a third current corresponding to a current flowing through the second pixel is calculated, wherein each the input transistor and the output transistor is a p-channel transistor, and wherein each of the first pixel and the second pixel includes an n-channel transistor. 5. The imaging device according to claim 4 , wherein current value of the second current is the same as current value of the first current. 6. The imaging device according to claim 4 , wherein the current flowing through the first pixel is a current corresponding to a state in which a charge retention portion included in the first pixel is initialized. 7. An imaging device comprising: a first pixel; a second pixel; and a current mirror circuit, wherein a first current corresponding to a current flowing through the first pixel flows to an input transistor of the current mirror circuit, wherein a light-blocking layer is arranged at a side where light enters a photoelectric conversion element included in the first pixel, wherein a second current flows to an output transistor of the current mirror circuit, and wherein a difference between the second current and a third current corresponding to a current flowing through the second pixel is calculated. 8. The imaging device according to claim 7 , wherein current value of the second current is the same as current value of the first current. 9. The imaging device according to claim 7 , wherein the current flowing through the first pixel is a current corresponding to a state in which a charge retention portion included in the first pixel is initialized. 10. The imaging device according to claim 7 , wherein each the input transistor and the output transistor is a p-channel transistor, wherein each of the first pixel and the second pixel includes an n-channel transistor.

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Classifications

  • characterised by the materials · CPC title

  • comprising only Group I-III-VI chalcopyrite materials, e.g. CuInSe2, CuGaSe2 or CuInGaSe2 [CIGS] · CPC title

  • comprising only selenium or only tellurium · CPC title

  • Optical shielding · CPC title

  • the integrated elements comprising a transistor · CPC title

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Frequently asked questions

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What does patent US10964743B2 cover?
A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.
Who is the assignee on this patent?
Semiconductor Energy Lab
What technology area does this patent fall under?
Primary CPC classification H10F39/18. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 30 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).