Imaging device and electronic device

Patent metadata

Field	Value
Publication number	US-11101302-B2
Application number	US-201816615156-A
Country	US
Kind code	B2
Filing date	May 16, 2018
Priority date	May 26, 2017
Publication date	Aug 24, 2021
Grant date	Aug 24, 2021

Abstract

An imaging device capable of image processing is provided.The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.

First claim

The invention claimed is:

1. An imaging device comprising:
a pixel block;
a first circuit; and
a second circuit,
wherein the pixel block comprises a plurality of pixels and a third circuit,
wherein the pixels and the third circuit are electrically connected to each other through a first wiring,
wherein the pixels have a function of obtaining a first signal by photoelectric conversion,
wherein the pixels have a function of multiplying the first signal by a predetermined multiplication factor to generate second signals and outputting the second signals to the first wiring,
wherein the third circuit has a function of calculating a sum of the second signals output to the first wiring to generate a third signal and outputting the third signal to the first circuit, and
wherein the first circuit binarizes the third signal to generate a fourth signal and outputs the fourth signal to the second circuit.

2. The imaging device according to claim 1 ,
wherein the second circuit has a function of performing parallel-serial conversion on the fourth signal.

3. The imaging device according to claim 1 ,
wherein the second circuit comprises a neural network which uses the fourth signal as input data.

4. The imaging device according to claim 1 ,
wherein the plurality of pixels are arranged in a matrix and any one column is shielded from light.

5. The imaging device according to claim 1 ,
wherein the pixels each comprise a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first capacitor,
wherein one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to a gate of the third transistor,
wherein the gate of the third transistor is electrically connected to one electrode of the first capacitor,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,
wherein the other electrode of the first capacitor is electrically connected to one of a source and a drain of the fourth transistor, and
wherein the first and second transistors comprise a metal oxide in their channel formation regions.

6. The imaging device according to claim 5 , further comprising:
a fifth transistor; and
a sixth transistor,
wherein a gate of the fifth transistor is electrically connected to the gate of the third transistor, and
wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor.

7. The imaging device according to claim 5 ,
wherein the third and fourth transistors comprise silicon in their channel formation regions.

8. The imaging device according to claim 1 ,
wherein the third circuit comprises a current supply circuit, a seventh transistor, an eighth transistor, a ninth transistor, a second capacitor, and a resistor,
wherein the current supply circuit is electrically connected to the first wiring,
wherein the first wiring is electrically connected to one electrode of the second capacitor,
wherein the one electrode of the second capacitor is electrically connected to one electrode of the resistor,
wherein the other electrode of the second capacitor is electrically connected to one of a source and a drain of the seventh transistor,
wherein the one of the source and the drain of the seventh transistor is electrically connected to a gate of the eighth transistor, and
wherein one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the ninth transistor.

9. The imaging device according to claim 8 ,
wherein the seventh to ninth transistors comprise silicon in their channel formation regions.

10. The imaging device according to claim 5 ,
wherein the metal oxide comprises In, Zn, and M,
wherein M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

11. The imaging device according to claim 5 ,
wherein the photoelectric conversion element comprises selenium or a compound containing selenium.

12. An electronic device comprising:
the imaging device according to claim 1 ; and
a display device.

Assignees

• Semiconductor Energy Lab

Inventors

• Ikeda Takayuki
• Kurokawa Yoshiyuki
• Harada Shintaro
• Kobayashi Hidetomo
• Yamamoto Roh
• Kimura Kiyotaka
• Nakagawa Takashi
• Negoro Yusuke

Classifications

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/46

  by combining or binning pixels · CPC title

• H04N25/766 Primary

  comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power · CPC title

• H04N25/40

  Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled · CPC title