Semiconductor device and electronic device
US-9870827-B2 · Jan 16, 2018 · US
Semiconductor device including oxide semiconductor
US10600839B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10600839-B2 |
| Application number | US-201816122060-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 5, 2018 |
| Priority date | Dec 10, 2014 |
| Publication date | Mar 24, 2020 |
| Grant date | Mar 24, 2020 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: memory elements arranged in a matrix of n rows and m columns, where each of n and m is a natural number of 2 or more, wherein each of the memory elements comprise a transistor whose channel formation region comprises an oxide semiconductor, and wherein the semiconductor device performs vector matrix multiplication while canceling an effect due to dark current of the memory elements. 2. The semiconductor device according to claim 1 , wherein the memory elements are configured to output pulse, depending on a threshold, so that the semiconductor device performs vector matrix multiplication. 3. A semiconductor device comprising: memory elements arranged in a matrix of n rows and m columns, where each of n and m is a natural number of 2 or more; and reference memory elements that are shielded from light, wherein each of the memory elements comprise a transistor whose channel formation region comprises an oxide semiconductor, and wherein the semiconductor device performs vector matrix multiplication while subtracting dark current of the reference memory elements. 4. The semiconductor device according to claim 3 , wherein the memory elements are configured to output pulse, depending on a threshold, so that the semiconductor device performs vector matrix multiplication. 5. A semiconductor device comprising: memory elements arranged in a matrix of n rows and m columns, where each of n and m is a natural number of 2 or more, wherein each of the memory elements comprise a transistor whose channel formation region comprises an oxide semiconductor, wherein the semiconductor device performs vector matrix multiplication while canceling an effect due to dark current of the memory elements, and wherein the semiconductor device performs smoothing processing, edge enhancement processing, or cosine transform by the vector matrix multiplication. 6. The semiconductor device according to claim 5 , wherein the memory elements are configured to output pulse, depending on a threshold, so that the semiconductor device performs vector matrix multiplication.
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
- H01L27/14643Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US10600839B2 cover?
- A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.
- Who is the assignee on this patent?
- Semiconductor Energy Lab
- What technology area does this patent fall under?
- Primary CPC classification H01L27/14643. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 24 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).