Imaging device and electronic device

Patent metadata

Field	Value
Publication number	US-10951850-B2
Application number	US-201816628914-A
Country	US
Kind code	B2
Filing date	Jul 2, 2018
Priority date	Jul 14, 2017
Publication date	Mar 16, 2021
Grant date	Mar 16, 2021

Abstract

An offset component of multiplication by a transistor is to be reduced. An imaging device includes a pixel region, a first circuit, a second circuit, a third circuit, and a fourth circuit. The pixel region includes a plurality of pixels, and a pixel includes a first transistor. An offset potential and a weight potential are supplied to the pixel selected by the first circuit and the second circuit. The pixel obtains a first signal by photoelectric conversion with use of light. The first transistor multiplies the first signal by the weight potential. The first transistor generates a first offset term and a second offset term with use of a multiplication term of the first signal by the weight potential and the offset potential. The third circuit subtracts the first offset term, and the fourth circuit subtracts the second offset term. The fourth circuit determines the multiplication term, and the fourth circuit outputs a determination result through the neural network interface.

First claim

The invention claimed is:

1. An imaging device comprising a neural network interface,
wherein:
the imaging device includes a pixel region, a first circuit, a second circuit, a third circuit, a fourth circuit, and a first signal line Wx,
the pixel region includes a plurality of pixels,
a pixel of the plurality of pixels includes a first transistor,
the fourth circuit includes the neural network interface,
the pixel is electrically connected to the third circuit through the first signal line Wx,
the third circuit is electrically connected to the fourth circuit,
the first circuit has a function of supplying a scan signal to the pixel,
the second circuit has a function of supplying a weight potential to the pixel selected by the scan signal,
the pixel has a function of obtaining a first signal by photoelectric conversion with use of light,
the pixel has a function of multiplying the first signal by the weight potential with use of the first transistor,
the first transistor has a function of generating a multiplication term of the first signal by the weight potential, a first offset term, and a second offset term,
the third circuit has a function of subtracting the first offset term,
the fourth circuit has a function of subtracting the second offset term,
the fourth circuit has a function of determining the multiplication term, and
the fourth circuit outputs a determination result through the neural network interface.

2. The imaging device according to claim 1 ,
wherein:
the second circuit also has a function of supplying an offset potential to the pixel selected by the scan signal,
the pixel has a function of generating a second signal by adding the offset potential to the first signal,
the pixel has a function of generating a third signal by adding the weight potential to the offset potential,
the pixel has a function of generating a fourth signal by adding the offset potential and the weight potential to the first signal,
the first transistor has a function of generating a fifth signal by multiplying the second signal by a given number,
the first transistor has a function of generating a sixth signal by multiplying the third signal by a given number,
the first transistor has a function of generating a seventh signal by multiplying the fourth signal by a given number,
the third circuit has a function of storing the second signal,
the third circuit has a function of generating an eighth signal by performing an operation on the seventh signal and the fifth signal,
the fourth circuit has a function of storing the eighth signal,
the fourth circuit has a function of generating a ninth signal by performing an operation on the eighth signal and the sixth signal,
the multiplication term of the first signal by the weight potential is output to the ninth signal,
the fourth circuit has a function of determining the ninth signal, and
the fourth circuit outputs a determination result through the neural network interface.

3. The imaging device according to or claim 2 , further comprising:
a second signal line Wx;
a signal line Bsel; and
a switch Bsw,
wherein:
the switch Bsw has a function of electrically connecting the first signal line Wx and the second signal line Wx in response to a signal supplied to the signal line Bsel,
the third circuit has a function of receiving a plurality of the fifth signals, a plurality of the sixth signals, and a plurality of the seventh signals from a plurality of the pixels connected to the first signal line Wx and a plurality of the pixels connected to the second signal line Wx,
the third circuit has a function of adding the fifth signal, the sixth signal, and the seventh signal supplied from each of the pixels and then subtracting the first offset term,
the imaging device has a function of selecting a selection range of a plurality of the pixels in response to a signal applied to the switch Bsw, and
pooling processing is performed in the imaging device in accordance with the selection range of the pixels.

4. The imaging device according to claim 1 ,
wherein:
the imaging device further includes an analog/digital converter circuit, a signal line Pio, and a wiring VRS,
the pixel has a function of outputting first data to the analog/digital converter circuit through the signal line Pio,
the pixel has a function of receiving, through the signal line Pio, a first potential supplied to the wiring VRS, and
the pixel functions as a neural network neuron when the first potential supplied to the wiring VRS is input to the pixel through the signal line Pio.

5. The imaging device according to claim 1 ,
wherein:
the imaging device further includes a wiring VPD, a wiring VDM, a signal line G 1 , a signal line G 2 , a signal line G 3 , a signal line Tx, a signal line Res, a signal line S 1 , and a signal line S 2 ,
the pixel includes a photoelectric conversion element, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor,
the first circuit is electrically connected to the pixel through the signal line G 1 ,
the first circuit is electrically connected to the pixel through the signal line G 2 ,
the first circuit is electrically connected to the pixel through the signal line G 3 ,
the second circuit is electrically connected to the pixel through the signal line S 1 ,
the second circuit is electrically connected to the pixel through the signal line S 2 ,
one electrode of the photoelectric conversion element is electrically connected to the wiring VPD,
the other electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the second transistor,
a gate of the second transistor is electrically connected to the signal line Tx,
the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, a gate of the fourth transistor, and one electrode of the first capacitor,
the other of the source and the drain of the third transistor is electrically connected to the wiring VRS,
a gate of the third transistor is electrically connected to the signal line Res,
one of a source and a drain of the fourth transistor is electrically connected to the wiring VDM,
the other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor and one electrode of the second capacitor,
the other of the source and the drain of the fifth transistor is electrically connected to the wiring Pio,
a gate of the fifth transistor is electrically connected to the signal line G 3 ,
the other electrode of the second capacitor is electrically connected to a gate of the first transistor, one of a source and a drain of the sixth transistor, and one electrode of the third capacitor,
one of a source and a drain of the first transistor is electrically connected to the first signal line Wx,
the other source and the drain of the sixth transistor is electrically connected to the signal line S 1 ,
a gate of the sixth transistor is electrically connected to the signal line G 1 ,
the other electrode of the third capacitor is electrically connected to one of a source and a drain of the seventh transistor,
the other of the source and the drain of the seventh transistor is electrically connected to the signal line S 2 , and
a gate of the seventh transistor is electrically connected to the signal line G 2 .

6. The imaging device according to claim 5 , further comprising:
a signal line Csw;
a signal line Cswb;
a signal line Eabs;
a signal line Osp;
a signal line Ewx;
a signal line Mac; and
a wiring VIV,
wherein

Assignees

• Semiconductor Energy Lab

Inventors

• Yamamoto Roh
• Fukutome Takahiro

Classifications

• G06N3/04 Primary

  Architecture, e.g. interconnection topology · CPC title

• G06N3/065

  Analogue means · CPC title

• H04N25/771 Primary

  comprising storage means other than floating diffusion · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title