Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-10074687-B2
Application number	US-201715708527-A
Country	US
Kind code	B2
Filing date	Sep 19, 2017
Priority date	Dec 10, 2014
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.

First claim

What is claimed is:

1. A semiconductor device comprising:
memory elements arranged in a matrix of n rows and m columns, where each of n and m is a natural number of 2 or more memory elements each including a first transistor, a second transistor, and a first capacitor;
a first circuit; and
a second circuit,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor,
wherein the gate electrode of the second transistor is electrically connected to one electrode of the first capacitor,
wherein the other electrode of the first capacitor is electrically connected to a first wiring provided in each row,
wherein a gate electrode of the first transistor is electrically connected to a second wiring provided in each row,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a third wiring provided in each column,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a fourth wiring provided in each column,
wherein the other of the source electrode and the drain electrode of the second transistor is electrically connected to a fifth wiring provided in each column,
wherein the first wiring is capable of supplying a different potential to each row,
wherein the fifth wirings electrically connected to the memory elements in the first to (m−1)th columns are each electrically connected to the first circuit,
wherein the fifth wiring electrically connected to memory elements in an m-th column is electrically connected to a first power supply line,
wherein one input terminal of the second circuit is electrically connected to the fifth wirings electrically connected to the memory elements in the first to (m−1)th columns and the first circuit through a first current mirror circuit, and
wherein the other input terminal of the second circuit is electrically connected to the fifth wiring electrically connected to the memory elements in the m-th column and the first circuit through a second current mirror circuit.

2. The semiconductor device according to claim 1 , wherein the first circuit functions as a constant-current circuit, and the second circuit functions as an output circuit.

3. The semiconductor device according to claim 1 ,
wherein the first circuit includes a third transistor, a fourth transistor, and a second capacitor,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor,
wherein the one of the source electrode and the drain electrode of the third transistor is electrically connected to the fifth wiring electrically connected to any of the memory elements in the first to (m−1)th columns,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one electrode of the second capacitor,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to a second power supply line,
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to a gate electrode of the third transistor, and
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the other electrode of the second capacitor.

4. The semiconductor device according to claim 3
wherein one of a source electrode and a drain electrode of an input transistor of the first current mirror circuit is electrically connected to the first power supply line,
wherein the other of the source electrode and the drain electrode of the input transistor of the first current mirror circuit is electrically connected to the fifth wiring electrically connected to the memory elements in any of the first to (m−1)th columns and the one of the source electrode and the drain electrode of the third transistor,
wherein one of a source electrode and a drain electrode of an output transistor of the first current mirror circuit is electrically connected to the first power supply line, and
wherein the other of the source electrode and the drain electrode of the output transistor of the first current mirror circuit is electrically connected to one input terminal of the second circuit.

5. The semiconductor device according to claim 1 ,
wherein one of a source electrode and a drain electrode of an input transistor of the second current mirror circuit is electrically connected to the first power supply line,
wherein the other of the source electrode and the drain electrode of the input transistor of the second current mirror circuit is electrically connected to the fifth wiring electrically connected to the memory elements in the m-th column,
wherein one of a source electrode and a drain electrode of an output transistor of the second current mirror circuit is electrically connected to the first power supply line, and
wherein the other of the source electrode and the drain electrode of the output transistor of the second current mirror circuit is electrically connected to the other input terminal of the second circuit.

6. The semiconductor device according to claim 1 ,
wherein the second circuit includes an operational amplifier, and
wherein one input terminal of the operational amplifier is electrically connected to a second power supply line through a first resistor.

7. The semiconductor device according to claim 1 ,
wherein the transistor included in the memory element and the first circuit includes an oxide semiconductor in an active layer, and
wherein the oxide semiconductor includes In, Zn, and M, where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

8. An electronic device comprising:
the semiconductor device according to claim 1 , and
a display device.

9. A semiconductor device comprising:
cells arranged in a matrix of n rows and m columns, where each of n and m is a natural number of 2 or more,
wherein the cells are configured to output pulse, depending on a threshold, so that the semiconductor device performs image processing by vector matrix multiplication.

10. The semiconductor device according to claim 9 , wherein each of cells comprise a transistor whose channel formation region comprising an oxide semiconductor.

Assignees

• Semiconductor Energy Lab

Inventors

• Kurokawa Yoshiyuki

Classifications

• H01L27/14643 Primary

  Electricity · mapped topic

• H01L27/14623

  Electricity · mapped topic

• H01L31/0272

  Electricity · mapped topic

• H01L31/0322

  Electricity · mapped topic

• H01L29/24

  Electricity · mapped topic