Reduced interfacial area III-nitride material semiconductor structures

Patent metadata

Field	Value
Publication number	US-11942518-B2
Application number	US-202117335521-A
Country	US
Kind code	B2
Filing date	Jun 1, 2021
Priority date	Jul 19, 2018
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

Semiconductor structures and devices in III-nitride materials are described herein, including material structures comprising III-nitride material regions (e.g., gallium nitride material regions). In certain cases, the material structures comprise substrates having relatively high electrical conductivities. In other cases, the material structures comprise substrates having relatively high resistivities. Certain embodiments include one or more features that reduce the degree to which thermal runaway occurs, which can enhance device performance including at elevated flange temperatures. Some embodiments include one or more features that reduce the degree of capacitive coupling exhibited during operation. For example, in some embodiments, relatively thick III-nitride material regions and/or relatively small ohmic contacts are employed.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a III-nitride material region located over the substrate;
an ohmic contact over the III-nitride material region, the ohmic contact defining an ohmic contact interfacial area with the III-nitride material region; and
a gate electrode over the III-nitride material region, the gate electrode defining a gate electrode interfacial area with the III-nitride material region, wherein
the ohmic contact interfacial area is less than 50 times the gate electrode interfacial area.

2. The semiconductor device of claim 1 , wherein at least a portion of the substrate has an electronic resistivity of less than 0.10 Ω-cm at 25° C.

3. The semiconductor device of claim 1 , wherein at least a portion of the substrate has an electronic resistivity of 10,000 Ω-cm at 25° C.

4. The semiconductor device of claim 1 , wherein at least a portion of the substrate comprises silicon.

5. The semiconductor device of claim 1 , wherein at least a portion of the substrate comprises silicon carbide.

6. The semiconductor device of claim 1 , wherein the substrate comprises a silicon-on-insulator structure.

7. The semiconductor device of claim 1 , wherein the substrate comprises a bulk silicon or a silicon carbide substrate.

8. The semiconductor device of claim 1 , wherein the III-nitride material region comprises gallium nitride materials.

9. The semiconductor device of claim 1 , wherein the III-nitride material region comprises:
a nucleation layer over the substrate;
a buffer layer over the nucleation layer; and
a device region over the buffer layer.

10. The semiconductor device of claim 9 , further comprising a transition layer located between the nucleation layer and the buffer layer.

11. The semiconductor device of claim 10 , wherein the transition layer comprises a superlattice.

12. The semiconductor device of claim 10 , wherein the transition layer is compositionally graded.

13. The semiconductor device of claim 1 , wherein the semiconductor device is a transistor or a diode.

14. The semiconductor device of claim 13 , wherein the transistor or diode is configured to operate at a frequency between 100 MHz and 20 GHz.

15. The semiconductor device of claim 1 , wherein:
the semiconductor device comprises a transistor;
the ohmic contact comprises a source ohmic contact of the transistor, the source ohmic contact defining a source ohmic contact interfacial area; and
the source ohmic contact interfacial area is less than 50 times the gate electrode interfacial area.

16. The semiconductor device of claim 15 , wherein the source ohmic contact interfacial area is less than 40 times the gate electrode interfacial area.

17. The semiconductor device of claim 15 , wherein the source ohmic contact interfacial area is less than 30 times the gate electrode interfacial area.

18. The semiconductor device of claim 1 , wherein:
the semiconductor device comprises a transistor;
the ohmic contact comprises a drain ohmic contact of the transistor, the drain ohmic contact defining a drain ohmic contact interfacial area; and
the drain ohmic contact interfacial area is less than 50 times the gate electrode interfacial area.

19. The semiconductor device of claim 18 , wherein:
the drain ohmic contact interfacial area is less than 40 times the gate electrode interfacial area.

20. The semiconductor device of claim 18 , wherein:
the drain ohmic contact interfacial area is less than 30 times the gate electrode interfacial area.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Boles Timothy E
• Struble Wayne Mack

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3216

  Nitrides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title