Method for producing a iii-n material-based layer
US-2024038532-A1 · Feb 1, 2024 · US
US9627473B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9627473-B2 |
| Application number | US-201514847325-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 8, 2015 |
| Priority date | Sep 8, 2015 |
| Publication date | Apr 18, 2017 |
| Grant date | Apr 18, 2017 |
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III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
Opening claim text (preview).
What is claimed is: 1. A semiconductor structure, comprising: a substrate comprising silicon; and a III-nitride material region located over a surface region of the substrate, a diffusion barrier region between the III-nitride material region and the substrate, wherein: the diffusion barrier region comprises at least one of a rare-earth oxide and/or a rare-earth nitride, the surface region of the substrate comprises a low-conductivity parasitic channel or the substrate is free of a parasitic channel, and at least a region of the substrate comprises at least one species having a relative atomic mass of less than 5 at a concentration of at least about 10 19 /cm 3 . 2. The semiconductor structure of claim 1 , wherein at least a portion of the surface region of the substrate comprises at least one species having a relative atomic mass of less than 5 at a concentration of at least about 10 19 /cm 3 . 3. The semiconductor structure of claim 1 , wherein the substrate comprises at least a layer having a resistivity of greater than about 10 2 Ohms-cm. 4. The semiconductor structure of claim 1 , wherein the substrate is a silicon substrate. 5. The semiconductor structure of claim 4 , wherein the substrate is a bulk silicon wafer. 6. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises GaN. 7. The semiconductor structure of claim 1 , wherein the species having a relative atomic mass of less than 5 comprises hydrogen and/or helium. 8. The semiconductor structure of claim 1 , wherein the species having a relative atomic mass of less than 5 is located within the substrate in a spatially defined pattern. 9. The semiconductor structure of 1 , wherein the surface region of the substrate comprises a low-conductivity parasitic channel. 10. The semiconductor structure of claim 9 , wherein the low-conductivity parasitic channel has a peak free carrier concentration that is less than about 10 17 /cm 3 . 11. The semiconductor structure of claim 9 , wherein the low-conductivity parasitic channel has a total integrated surface region charge of less than about 10 12 /cm 2 . 12. The semiconductor structure of claim 9 , wherein the substrate comprises a bulk region below the surface region, the bulk region having a lower peak free carrier concentration than the surface region. 13. The semiconductor structure of claim 12 , wherein the bulk region is doped with a first free carrier type and the surface region is doped with a second free carrier type. 14. The semiconductor structure of claim 12 , wherein the peak free carrier concentration in the bulk region is less than about 10 13 /cm 3 . 15. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride nucleation layer. 16. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride transition layer. 17. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride buffer layer. 18. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride device region.
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