Parasitic channel mitigation using rare-earth oxide and/or rare-earth nitride diffusion barrier regions

US9673281B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9673281-B2
Application numberUS-201514847265-A
CountryUS
Kind codeB2
Filing dateSep 8, 2015
Priority dateSep 8, 2015
Publication dateJun 6, 2017
Grant dateJun 6, 2017

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Abstract

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III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

First claim

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What is claimed is: 1. A semiconductor structure, comprising: a substrate comprising silicon and comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm; a diffusion barrier region comprising an erbium oxynitride, a gadolinium oxynitride, a cerium oxynitride, and/or a yttrium oxynitride located over a surface of the substrate; and a III-nitride material region located over the diffusion barrier region. 2. The semiconductor structure of claim 1 , wherein the diffusion barrier region has a thickness of less than about 200 nm. 3. The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Group III species in the substrate is less than about 10 17 /cm 3 . 4. The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Al, Ga, and In in the substrate is less than about 10 17 /cm. 5. The semiconductor structure of claim 1 , wherein the peak concentration of Al, Ga, and/or In in the substrate is less than about 10 17 /cm 3 . 6. The semiconductor structure of claim 1 , wherein the substrate comprises a surface region associated with the surface of the substrate, and the surface region comprises a low-conductivity parasitic channel or the substrate is free of a parasitic channel. 7. The semiconductor structure of claim 6 , wherein the low-conductivity parasitic channel has a total integrated surface region charge of less than about 10 12 /cm 2 . 8. The semiconductor structure of claim 6 , wherein the low-conductivity parasitic channel has a peak free carrier concentration that is less than about 10 17 /cm 3 . 9. The semiconductor structure of claim 1 , wherein the substrate is a silicon substrate. 10. The semiconductor structure of claim 9 , wherein the substrate is a bulk silicon wafer. 11. The semiconductor structure of claim 1 , wherein the substrate is a silicon carbide substrate. 12. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises GaN. 13. The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a transistor located over the substrate. 14. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride device region. 15. A method of forming a semiconductor structure, comprising: forming a diffusion barrier region comprising an erbium oxynitride, a gadolinium oxynitride, a cerium oxynitride, and/or a yttrium oxynitride over a substrate comprising silicon, the substrate comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm; and forming a III-nitride material region over the diffusion barrier region. 16. A semiconductor structure comprising: a silicon-on-insulator substrate and comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm; a diffusion barrier region comprising a rare-earth oxide and/or a rare-earth nitride located over a surface of the substrate; and a III-nitride material region located over the diffusion barrier region.

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What does patent US9673281B2 cover?
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
Who is the assignee on this patent?
M/A-Com Tech Solutions Holdings Inc, Macom Tech Solutions Holdings Inc
What technology area does this patent fall under?
Primary CPC classification H01L29/1054. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 06 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).