Transistor contacts and methods of forming the same
US-2024395871-A1 · Nov 28, 2024 · US
US9673281B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9673281-B2 |
| Application number | US-201514847265-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 8, 2015 |
| Priority date | Sep 8, 2015 |
| Publication date | Jun 6, 2017 |
| Grant date | Jun 6, 2017 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
Opening claim text (preview).
What is claimed is: 1. A semiconductor structure, comprising: a substrate comprising silicon and comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm; a diffusion barrier region comprising an erbium oxynitride, a gadolinium oxynitride, a cerium oxynitride, and/or a yttrium oxynitride located over a surface of the substrate; and a III-nitride material region located over the diffusion barrier region. 2. The semiconductor structure of claim 1 , wherein the diffusion barrier region has a thickness of less than about 200 nm. 3. The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Group III species in the substrate is less than about 10 17 /cm 3 . 4. The semiconductor structure of claim 1 , wherein the peak of the sum of the concentrations of Al, Ga, and In in the substrate is less than about 10 17 /cm. 5. The semiconductor structure of claim 1 , wherein the peak concentration of Al, Ga, and/or In in the substrate is less than about 10 17 /cm 3 . 6. The semiconductor structure of claim 1 , wherein the substrate comprises a surface region associated with the surface of the substrate, and the surface region comprises a low-conductivity parasitic channel or the substrate is free of a parasitic channel. 7. The semiconductor structure of claim 6 , wherein the low-conductivity parasitic channel has a total integrated surface region charge of less than about 10 12 /cm 2 . 8. The semiconductor structure of claim 6 , wherein the low-conductivity parasitic channel has a peak free carrier concentration that is less than about 10 17 /cm 3 . 9. The semiconductor structure of claim 1 , wherein the substrate is a silicon substrate. 10. The semiconductor structure of claim 9 , wherein the substrate is a bulk silicon wafer. 11. The semiconductor structure of claim 1 , wherein the substrate is a silicon carbide substrate. 12. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises GaN. 13. The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a transistor located over the substrate. 14. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride device region. 15. A method of forming a semiconductor structure, comprising: forming a diffusion barrier region comprising an erbium oxynitride, a gadolinium oxynitride, a cerium oxynitride, and/or a yttrium oxynitride over a substrate comprising silicon, the substrate comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm; and forming a III-nitride material region over the diffusion barrier region. 16. A semiconductor structure comprising: a silicon-on-insulator substrate and comprising at least a layer having a resistivity of greater than 10 2 Ohms-cm; a diffusion barrier region comprising a rare-earth oxide and/or a rare-earth nitride located over a surface of the substrate; and a III-nitride material region located over the diffusion barrier region.
of electrically inactive species · CPC title
into Group IV semiconductors · CPC title
using masks · CPC title
Nitrides · CPC title
being group IIIA-VIA materials · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.