Semiconductor device, high electron mobility transistor (hemt) and method of manufacturing
US-2015041825-A1 · Feb 12, 2015 · US
US9773898B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9773898-B2 |
| Application number | US-201514847290-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 8, 2015 |
| Priority date | Sep 8, 2015 |
| Publication date | Sep 26, 2017 |
| Grant date | Sep 26, 2017 |
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III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.
Opening claim text (preview).
What is claimed is: 1. A semiconductor structure, comprising: a silicon-on-insulator substrate; a III-nitride material region located over a surface region of the substrate; and an implanted species arranged within the surface region of the substrate in a pattern spatially defined across at least one lateral dimension of the substrate, wherein the implanted species is present within at least a portion of the surface region of the substrate at a concentration of at least about 10 19 /cm 3 . 2. The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a transistor located over the substrate. 3. The semiconductor structure of claim 2 , wherein at least a portion of the substrate underneath a channel between a source of the transistor and a drain of the transistor is substantially free of the implanted species. 4. The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a second transistor laterally spaced apart from a first transistor, wherein a portion of the surface region of the substrate between the first transistor and the second transistor has a concentration of the implanted species of at least about 10 19 /cm 3 . 5. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a 2DEG region, and the 2DEG region is substantially free of the implanted species. 6. The semiconductor structure of claim 1 , wherein the substrate comprises at least a layer having a resistivity of greater than about 10 2 Ohms-cm. 7. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises GaN. 8. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride nucleation layer. 9. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride transition layer. 10. The semiconductor structure of claim 9 , wherein the III-nitride transition layer is compositionally graded. 11. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride buffer layer. 12. The semiconductor structure of claim 1 , wherein the III-nitride material region comprises a III-nitride device region. 13. The semiconductor structure of claim 1 , wherein a diffusion barrier region is located between the III-nitride material region and the substrate.
for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673) · CPC title
Nitride Group III-V materials, e.g. AlN or GaN · CPC title
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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