Parasitic channel mitigation via back side implantation

Patent metadata

Field	Value
Publication number	US-9799520-B2
Application number	US-201514847240-A
Country	US
Kind code	B2
Filing date	Sep 8, 2015
Priority date	Sep 8, 2015
Publication date	Oct 24, 2017
Grant date	Oct 24, 2017

Abstract

III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates. Certain embodiments are related to gallium nitride materials and material structures comprising gallium nitride material regions and silicon-containing substrates.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
implanting a species having a relative atomic mass of less than 5 into a structure comprising a III-nitride material region and a substrate comprising silicon,
wherein at least a portion of the species is implanted through the substrate to produce a surface region at a top surface of the substrate without being implanted through the III-nitride material region,
wherein the top surface of the substrate is at the interface of the III-nitride material region and the substrate, and
implanting the species produces the surface region comprising no parasitic channel or a low-conductivity parasitic channel.

2. The method of claim 1 , wherein the substrate comprises at least a layer having a resistivity of greater than about 10 2 Ohms-cm.

3. The method of claim 1 , wherein the substrate is a silicon substrate.

4. The method of claim 3 , wherein the substrate is a bulk silicon wafer.

5. The method of claim 3 , wherein the substrate is a silicon-on-insulator substrate.

6. The method of claim 1 , wherein the substrate is a silicon carbide substrate.

7. The method of claim 1 , wherein the III-nitride material region comprises GaN.

8. The method of claim 1 , wherein the species having a relative atomic mass of less than 5 comprises hydrogen and/or helium.

9. The method of claim 1 , wherein the semiconductor structure comprises a transistor located over the surface region of the substrate.

10. The method of claim 1 , wherein after the implantation step, the semiconductor structure comprises a 2DEG region, and the 2DEG region is substantially free of the species having a relative atomic mass of less than 5.

11. The method of claim 1 , wherein implanting the species having a relative atomic mass of less than 5 into the substrate produces a surface region comprising a low-conductivity parasitic channel.

12. The method of claim 11 , wherein the low-conductivity parasitic channel has a peak free carrier concentration that is less than about 10 17 /cm 3 .

13. The method of claim 11 , wherein the low-conductivity parasitic channel has a total integrated surface region charge of less than about 10 12 /cm 2 .

14. The method of claim 1 , wherein, after the implanting step, the substrate comprises a bulk region below the surface region, the bulk region having a lower peak free carrier concentration than the surface region.

15. The method of claim 1 , wherein the III-nitride material region comprises a III-nitride device region.

16. The method of claim 1 , wherein, before the implanting step, the substrate comprises a surface region comprising a high-conductivity parasitic channel.

17. The method of claim 16 , wherein, before the implanting step, the substrate comprises a bulk region below the surface region, the bulk region having a lower peak free carrier concentration than the surface region.

18. The method of claim 17 , wherein the bulk region is doped with a first free carrier type and the surface region is doped with a second free carrier type.

19. The method of claim 18 , wherein the second free carrier type is Al and/or Ga.

20. The method of claim 17 , wherein the peak free carrier concentration in the bulk region is less than about 10 13 /cm 3 .

21. The method of claim 1 , wherein the substrate has a thickness of less than 50 microns.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Roberts John Claassen

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/208

  of electrically inactive species · CPC title