Thermal dissipation in semiconductor devices

Patent metadata

Field	Value
Publication number	US-11942390-B2
Application number	US-202217833288-A
Country	US
Kind code	B2
Filing date	Jun 6, 2022
Priority date	Apr 28, 2020
Publication date	Mar 26, 2024
Grant date	Mar 26, 2024

Abstract

A device includes a device layer comprising a first transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric layer on the backside of the device layer; a contact extending through the first dielectric layer to a source/drain region of the first transistor; a conductive line electrically connected to the source/drain region of the first transistor through the contact; and a thermal dissipation path thermally connected to the device layer, the thermal dissipation path extending to a surface of the second interconnect structure opposite the device layer. The thermal dissipation path comprises a dummy via.

First claim

What is claimed is:

1. A method comprising:
forming a transistor on a semiconductor substrate;
thinning the semiconductor substrate to expose a source/drain region of the transistor;
after thinning the semiconductor substrate, forming a first interconnect structure on a backside of the transistor, wherein forming the first interconnect structure comprises:
depositing a first dielectric layer on a backside of the transistor;
forming a contact through the first dielectric layer, the contact is electrically connected to a source/drain region of the transistor;
forming a conductive line electrically connected to the contact; and
forming a thermal dissipation path from the conductive line to a surface of the first interconnect structure opposite the transistor, wherein the thermal dissipation path comprises a dummy via; and

forming an external connector over the first interconnect structure, the external connector is thermally connected to the conductive line through the dummy via.

2. The method of claim 1 , wherein the conductive line is a power rail.

3. The method of claim 1 , further comprising forming a passive device in the first interconnect structure, wherein the dummy via extends between stacked portions of the passive device.

4. The method of claim 3 , wherein the dummy via has a same material composition as the passive device.

5. The method of claim 3 , wherein the passive device is an inductor.

6. The method of claim 1 further comprising:
prior to thinning the semiconductor substrate, forming a second interconnect structure on a front-side of the semiconductor substrate; and
bonding a carrier substrate to a surface of the second interconnect structure opposite the semiconductor substrate.

7. The method of claim 1 , wherein the thermal dissipation path is thermally connected to the transistor.

8. A method comprising:
forming a device layer on a semiconductor substrate, the device layer comprising a transistor;
forming a first interconnect structure over the device layer;
forming a second interconnect structure on an opposite side of the device layer as the first interconnect structure, wherein forming the second interconnect structure comprises:
depositing a first dielectric layer on a backside of the transistor;
forming a conductive line over the first dielectric layer and electrically connected to a source/drain region of the transistor; and
forming one or more layers of conductive features over the conductive line, wherein the one or more layers of conductive features comprises a dummy via thermally connected to the conductive line.

9. The method of claim 8 , wherein forming the second interconnect structure further comprises:
etching a first opening in the first dielectric layer to expose the source/drain region of the transistor; and
forming a first source/drain contact in the first opening.

10. The method of claim 9 , wherein forming the first interconnect structure comprises:
depositing a second dielectric layer on a front side of the transistor;
etching a second opening in the second dielectric layer, the second opening overlapping the source/drain region of the transistor; and
forming a contact in the second opening.

11. The method of claim 10 , wherein the contact is electrically isolated from the source/drain region of the transistor.

12. The method of claim 8 , wherein the one or more layers of conductive features comprises a passive device, wherein the dummy via is disposed between a first portion of the passive device and a second portion of the passive device, and wherein the first portion of the passive device is vertically stacked with the second portion of the passive device.

13. The method of claim 12 , wherein the passive device is an inductor.

14. The method of claim 8 , wherein the conductive line is a power line.

15. The method of claim 8 , wherein forming the second interconnect structure further comprises removing at least a portion of the semiconductor substrate.

16. A method comprising:
forming a device layer comprising a transistor on a semiconductor substrate;
forming a first interconnect structure on a front side of the device layer; and
forming a second interconnect structure on a backside of the device layer, forming the second interconnect structure comprising:
removing at least a portion of the semiconductor substrate;
forming a source/drain contact electrically connected to a source/drain region of the transistor;
forming a power rail electrically connected to the source/drain region by the source/drain contact; and
forming a dummy via thermally connecting the device layer to a surface of the second interconnect structure opposite to the device layer.

17. The method of claim 16 , wherein forming the second interconnect structure further comprises forming a passive device, wherein the dummy via is disposed between vertically stacked portions of the passive device.

18. The method of claim 16 , wherein removing at least the portion of the semiconductor substrate comprises applying a planarization process and an etch back process to the semiconductor substrate.

19. The method of claim 16 , wherein forming the first interconnect structure comprises forming a second source/drain contact electrically connected to a second source/drain region of the transistor.

20. The method of claim 16 , wherein forming the first interconnect structure comprises forming a dummy contact overlapping the source/drain region of the transistor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Wen-Sheh
• Chen Yu-Hsiang
• Chen Chii-Ping

Classifications

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title