Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters

Patent metadata

Field	Value
Publication number	US-11901037-B2
Application number	US-202318157945-A
Country	US
Kind code	B2
Filing date	Jan 23, 2023
Priority date	Apr 7, 2014
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

First claim

What is claimed is:

1. An apparatus, comprising:
a first plurality of mode registers configured to store a plurality of parameter codes for one of a plurality of operating parameters, each of the first plurality of mode registers storing the plurality of parameter codes for a different operating parameter of the plurality of operating parameters than other ones of the first plurality of mode registers; and
a second mode register configured to store a parameter code for a control parameter to select one of the plurality of parameter codes to set a current operating condition for the plurality of operating parameters.

2. The apparatus of claim 1 wherein at least one of the plurality of operating parameters comprises a burst length operating parameter, a preamble operating parameter, a precharge operating parameter, a postamble operating parameter, a latency parameter, a drive strength parameter, a data bus interface operating parameter, an on-die termination operating parameter, or a voltage reference operating parameter.

3. The apparatus of claim 1 , wherein the plurality of operating parameters comprises a burst length operating parameter, a preamble operating parameter, a precharge operating parameter, a postamble operating parameter, a latency parameter, a drive strength parameter, a data bus interface operating parameter, an on-die termination operating parameter, or a voltage reference operating parameter.

4. The apparatus of claim 1 , wherein the current operating condition is one of a plurality of operating conditions, wherein the plurality of operating conditions comprise a corresponding plurality of frequency set points.

5. A method, comprising:
storing in a first register associated with a mode register a first parameter code for a first operating parameter used to set a first memory operating condition;
storing in a second register associated with the mode register a second parameter code for the first operating parameter used to set a second memory operating condition;
storing in a third register associated with the mode register a third parameter code for a second operating parameter used to set the first memory operating condition;
storing in a fourth register associated with the mode register a fourth parameter code for the second operating parameter used to set the second memory operating condition; and
setting a current memory operating condition based on the first and third parameter codes or the second and fourth parameter codes.

6. The method of claim 5 , wherein the mode register comprises a first mode register, and the method further comprises storing a parameter code to a register associated with a second mode register, the parameter code indicative of the parameter code for the operating parameter to use for setting a current operation condition for a memory.

7. The method of claim 5 , wherein the mode register comprises a first mode register, and the method further comprises:
storing a parameter code having a first logic value to a register associated with a second mode register, wherein the first logic value of the parameter code selects the first and third parameter codes to set a current operating condition for a memory; and
storing the parameter code having a second logic value to the register associated with the second mode register, wherein the second logic value of the parameter code selects the second and fourth parameter codes to set the current operating condition for the memory.

8. The method of claim 5 , wherein setting the current memory operation condition comprises switching from the first and second parameter codes for the first operating and second parameters to the third and fourth parameter codes for the first and second operating parameters simultaneously.

9. The method of claim 5 , wherein the operating parameter comprises at least one of a voltage reference operating parameter and an on-die termination operating parameter.

10. The method of claim 5 , wherein the first memory operating condition and the second memory operating condition comprise different operating frequencies.

11. A method, comprising:
determining a first parameter code for a first operating parameter for a first operating condition of a memory;
writing to the memory the first parameter code to a first register for the first operating parameter;
determining a second parameter code for the first operating parameter for a second operating condition of the memory;
writing to the memory the second parameter code to a second register for the first operating parameter,
determining a third parameter code for a second operating parameter for the first operating condition of a memory;
writing to the memory the third parameter code to a third register for the second operating parameter;
determining a fourth parameter code for the second operating parameter for the second operating condition of the memory; and
writing to the memory the fourth parameter code to a fourth register for the second operating parameter.

12. The method of claim 11 , further comprising writing a parameter code to a mode register to set using the first parameter code for a current memory operating condition for the operating parameter.

13. The method of claim 11 , further comprising allowing a memory to initialize and set a default operating condition for a current memory operating condition.

14. The method of claim 11 , further comprising writing a parameter code to a mode register to set writing to the second register responsive to a mode register write operation prior to writing the second parameter code for the operating parameter.

15. The method of claim 11 , further comprising writing a parameter code to a mode register to set using the second parameter code for a current memory operating condition for the operating parameter subsequent to writing the second parameter code to the second register for the operating parameter.

16. The method of claim 11 , wherein the first operating condition is associated with memory operation according to a first clock frequency, and the second operating condition is associated with memory operation according to a second clock frequency that is different than the first clock frequency.

17. The method of claim 11 , wherein determining a first parameter code for an operating parameter for a first operating condition of the memory comprises:
performing a training routine with the memory for the first operating condition of the memory; and
determining the first parameter code for the operating parameter based on the training routine.

18. The method of claim 11 , wherein the first and second registers are associated with a mode register, and wherein writing to the memory the first parameter code to the first register for the operating parameter comprises writing the first parameter code to a mode register address associated with the mode register, and wherein writing to the memory the second parameter code to the second register for the operating parameter comprises writing the second parameter code to the mode register address associated with the mode register.

19. The method of claim 11 , wherein the operating parameter comprises at least one of a burst length operating parameter, a preamble operating parameter, a precharge operating parameter, a postamble operating parameter, a latency parameter, a drive strength parameter, a data bus interface operating parameter, an on-die termination operating parameter, and a voltage reference operating parameter.

20. The method of claim 11 , further com

Assignees

• Lodestar Licensing Group Llc

Inventors

• Gans Dean D
• Skinner Daniel C

Classifications

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title