Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters

Patent metadata

Field	Value
Publication number	US-10157647-B2
Application number	US-201815933167-A
Country	US
Kind code	B2
Filing date	Mar 22, 2018
Priority date	Apr 7, 2014
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

First claim

What is claimed is:

1. An apparatus comprising:
a mode register comprising:
a first register,
a second register,
a third register configured to store a first control parameter used to select between the first and second registers, and
a fourth register configured to store a second control parameter used to select between the first and second registers; and

a control logic circuit coupled to the mode register;
wherein the control logic circuit is configured to:
write a first parameter code to the first register under the first control parameter selecting the first register, and
write a second parameter code to the second register under the first control parameter selecting the second register; and

wherein the control logic circuit is further configured to:
set a first memory operating condition based, at least in part, on the first parameter code under the second control parameter selecting the first register, and
set a second memory operating condition based, at least in part, on the second parameter code under the second control parameter selecting the second register.

2. The apparatus of claim 1 , wherein the mode register further comprises fifth and sixth registers, and the control logic circuit is further configured to:
write a third parameter code to the fifth register when the first control parameter selects the third register; and
write a fourth parameter code to the sixth register when the first control parameter selects the fourth register,
wherein the first memory operating condition is further based on the third parameter code, and
wherein the second memory operating condition is further based on the fourth parameter code.

3. The apparatus of claim 1 , wherein the first register and the second register have a same mode register address.

4. The apparatus of claim 1 , wherein the first memory operating condition is related to operation at a first clock frequency and the second memory operating condition is related to operation at a second clock frequency.

5. A method comprising:
storing a first control parameter to a first register in a mode register, the mode register further including a second register, a third register and a fourth register, the first control parameter being used to select between the third and fourth registers;
storing a second control parameter to the second register in the mode register, the second control parameter being used to select between the third and fourth registers;
storing a first parameter code to the third register under the first control parameter selecting the third register;
storing a second parameter code to the fourth register under the first control parameter selecting the fourth register;
setting a first memory operation condition based, at least in part, on the first parameter code under the second control parameter selecting the third register; and
setting a second memory operation condition based, at least in part, on the second parameter code under the second control parameter selecting the fourth register.

6. The method of claim 5 , further comprising entering a training mode to determine values for at least one of the first and second parameter codes.

7. The method of claim 5 , wherein the first parameter code and the second parameter code are related to a same mode register parameter.

8. The method of claim 7 , wherein the mode register parameter comprises a latency parameter, a data bus inversion (DBI) parameter, an on-die termination (ODT) parameter, or a reference voltage parameter.

9. An apparatus comprising:
a first mode register including first and second registers using a same first mode register address;
a second mode register including third and fourth registers using a same second mode register address, wherein, when a value is written to the fourth register, one of first and second parameters is written to one of the first and second registers, respectively; and
a control logic circuit coupled to the first, second, third, and fourth registers, and configured to write the one of the first and second parameters to the one of the first and second registers, respectively, based on the value written to the fourth register.

10. The apparatus of claim 9 , wherein, when another value is written to the third register, one of first and second set points of a mode register parameter is selected based on the another value written to the third register.

11. The apparatus of claim 9 , further comprising fifth and sixth registers using a same third mode register address, wherein one of a third parameter and a fourth parameter is written to one of the fifth and sixth registers, respectively, based on the value written to the fourth register.

12. The apparatus of claim 9 , wherein the control logic circuit is further configured to write the one of the first and second parameters to the one of the first and second registers, respectively, responsive to a data write to mode register operation for the first mode register.

13. The apparatus of claim 9 , wherein the one of the first and second parameters written to the one of the first and second registers, respectively, is for a set point of a mode register parameter.

14. The apparatus of claim 9 , wherein the first and second parameters are related to a same mode register parameter, and
wherein the mode register parameter comprises a latency parameter, a data bus inversion (DBI) parameter, an on-die termination (ODT) parameter, or a reference voltage parameter.

15. The apparatus of claim 9 , wherein the one of the first and second parameters is of one of first and second set points for a same mode register parameter among a plurality of mode register parameters.

16. The apparatus of claim 9 , wherein the one of the first and second parameters is written to the one of the first and second registers for selecting between first and second set points, respectively, of a mode register parameter, and wherein the first and second set points are SP0 and SP1 of PARAMB, respectively.

17. The apparatus of claim 9 , wherein the one of the first and second parameters is written to the one of the first and second registers for selecting between first and second set points, respectively, of a mode register parameter, and wherein the mode register parameter is one of PARAMA, PARAMB, and PARAMC.

18. The apparatus of claim 9 , further comprising fifth and sixth registers using the same first mode register address.

19. A method comprising:
writing one of first and second parameters to one of first and second registers, respectively, using a same first mode register address;
writing at least one of first and second values to one of a third and fourth registers, respectively, using a same second mode register address, wherein, when the second value is written to the fourth register, the second value written to the fourth register is used to select between the first and second registers for the writing of the one of the first and second parameters, respectively; and
selecting, when the first value is written to the third register, one of first and second set points of a mode register parameter, based on the first value written to the third register.

20. The method of claim 19 , wherein the mode register parameter comprises a latency parameter, a data bus inversion (DBI) parameter, an on-die termination (ODT) parameter, or a reference voltage parameter.

21. The method of claim 19 , further comprising writing, based on the second value written to the fourth register, one of third and

Assignees

• Micron Technology Inc

Inventors

• Gans Dean D
• Skinner Daniel C

Classifications

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title