Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters

Patent metadata

Field	Value
Publication number	US-10424351-B2
Application number	US-201816222806-A
Country	US
Kind code	B2
Filing date	Dec 17, 2018
Priority date	Apr 7, 2014
Publication date	Sep 24, 2019
Grant date	Sep 24, 2019

Abstract

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

First claim

What is claimed is:

1. A method for operating a memory device, comprising:
receiving a first memory command that is issued outside of the memory device; the memory device comprising first and second mode registers, the first mode register being identified by a first mode register address and comprising first and second registers, and the second mode register being identified by a second mode register address and comprising a third register; and
performing, responsive to the first memory command being a mode register write command for the first mode register, a mode register write operation to the first mode register address, wherein the performing the mode register write operation to the first mode register address comprises writing first data associated with the mode register write command for the first mode register to the first register when the third register is at a first write-selection value and to the second register when the third register is at a second write-selection value.

2. The method of claim 1 , further comprising:
receiving a second memory command that is issued outside the memory device; and
performing, responsive to the second memory command being a mode register write command for the second mode register, a mode register write operation to the second mode register address, wherein the performing the mode register write operation to the second mode register address comprises writing second data associated with the mode register write command for the second mode register to the third register to set the third register to one of the first and second write-selection values.

3. The method of claim 2 , wherein the first and second memory commands are issued by a memory controller provided outside the memory device and the memory device receives the first and second memory commands through a bus between the memory controller and the memory device.

4. The method of claim 2 ,
wherein the second mode register further comprises a fourth register; and
wherein the method further comprises setting a first memory operating condition based, at least in part, on the first register when the fourth register is at a first condition-selection value and a second memory operating condition based, at least in part, on the second register when the fourth register is at a second condition-selection value.

5. The method of claim 4 ,
wherein the performing the mode register write operation to the second mode register address further comprises writing third data associated with the mode register write command for the second mode register to the fourth register to set the fourth register to one of the first and second condition-selection values.

6. The method of claim 1 , further comprises setting one of first and second memory operating conditions, the first memory operating condition being based, at least in part, on the first register and the second memory operating condition being based, at least in part, on the second register.

7. The method of claim 6 , further comprising receiving a clock signal at a first frequency under the first memory operating condition and at a second frequency under the second memory operating condition.

8. The method of claim 7 , wherein the first register stores one or more of a burst length parameter, a preamble parameter, a precharge parameter, a postamble parameter, a latency parameter, a drive strength parameter; a data bus inversion parameter, an on-die termination parameter and a reference voltage parameter under the first memory operating condition, and the second register stores one or more of a burst length parameter, a preamble parameter, a precharge parameter, a postamble parameter, a latency parameter, a drive strength parameter, a data bus inversion parameter, an on-die termination parameter and a reference voltage parameter under the second memory operating condition.

9. A method for operating a memory device, comprising:
receiving a first memory command that is issued outside of the memory device, the memory device comprising first and second mode registers, the first mode register being identified by a first mode register address and comprising first and second registers; and the second mode register being identified by a second mode register address and comprising a third register;
performing, responsive to the first memory command being a mode register write command for the second mode register, a mode register write operation to the second mode register address, wherein the performing the mode register write operation to the second mode register address comprises writing first data associated with the mode register write command for the second mode register to the third register to set the third register to one of first and second condition-selection values; and
setting a first memory operating condition based, at least in part, on the first register when the third register is at the first condition-selection value and a second memory operating condition based, at least in part; on the second register when the third register is at the second condition-selection value.

10. The method of claim 9 ,
wherein the second mode register further comprises a fourth register; and
wherein the method further comprises:
receiving a second memory command that is issued outside the memory device; and
performing, responsive to the second memory command being a mode register write command for the first mode register, a mode register write operation to the first mode register address, wherein the performing the mode register write operation to the first mode register address comprises writing second data associated with the mode register write command for the first mode register to the first register when the fourth register is at a first write-selection value and to the second register when the fourth register is at a second write-selection value.

11. The method of claim 10 , wherein the first and second memory commands are issued by a memory controller provided outside the memory device and the memory device receives the first and second memory commands through a bus between the memory controller and the memory device.

12. The method of claim 10 ,
wherein the performing the mode register write operation to the second mode register address further comprises writing third data associated with the mode register write command for the second mode register to the fourth register to set the fourth register to one of the first and second write-selection values.

13. The method of claim 9 , further comprising receiving a clock signal at a first frequency under the first memory operating condition and at a second frequency under the second memory operating condition.

14. The method of claim 13 , wherein the first register stores one or more of a burst length parameter, a preamble parameter, a precharge parameter, a postamble parameter, a latency parameter, a drive strength parameter, a data bus inversion parameter, an on-die termination parameter and a reference voltage parameter under the first memory operating condition, and the second register stores one or more of a burst length parameter, a preamble parameter, a precharge parameter, a postamble parameter, a latency parameter, a drive strength parameter, a data bus inversion parameter, an on-die termination parameter and a reference voltage parameter under the second memory operating condition.

15. A method for operating a memory device, comprising:
receiving a first memory command that is issued outside of the memory device, the memory device comprising first and second mode registers, the first mode register being identified by a first mode

Assignees

• Micron Technology Inc

Inventors

• Gans Dean D
• Skinner Daniel C

Classifications

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title