Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters

Patent metadata

Field	Value
Publication number	US-9934831-B2
Application number	US-201414247129-A
Country	US
Kind code	B2
Filing date	Apr 7, 2014
Priority date	Apr 7, 2014
Publication date	Apr 3, 2018
Grant date	Apr 3, 2018

Abstract

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

First claim

What is claimed is:

1. An apparatus, comprising:
a first mode register including a first register configured to store a first parameter code for an operating parameter and further including a second register configured to store a second parameter code for the operating parameter;
a second mode register including a third register configured to store a parameter code for a first control parameter used to select between the first parameter code stored by the first register and the second parameter code stored by the second register to set a current memory operating condition, the second mode register further including a fourth register configured to store a parameter code for a second control parameter used to select between the first register and the second register to write a parameter code for the operating parameter; and
a control logic circuit coupled to the first and second mode registers and configured to set the current memory operating condition from the stored parameter codes for the operating parameter based on the parameter code for the control parameter stored by the third register.

2. The apparatus of claim 1 wherein the first register is configured to store a first parameter code for the operating parameter having a plurality of bits.

3. The apparatus of claim 1 wherein the operating parameter comprises a first operating parameter, and wherein the first mode register further includes a fifth register configured to store a first parameter code for a second operating parameter and further includes a fifth register configured to store a second parameter code for the second operating parameter.

4. The apparatus of claim 3 wherein the control logic circuit is further configured to switch from the first parameter codes of the first and second operating parameters to the second parameter codes of the first and second operating parameters simultaneously.

5. The apparatus of claim 1 wherein the operating parameter comprises a first operating parameter, and the apparatus further comprises a third mode register including a fifth register configured to store a first parameter code for a second operating parameter and further includes a fifth register configured to store a second parameter code for the second operating parameter.

6. The apparatus of claim 1 wherein the control logic circuit is further configured to write a parameter code for the operating parameter to one of the first and second registers based on the parameter code for the second control parameter responsive to a mode register write operation for the first mode register.

7. The apparatus of claim 1 wherein the control logic circuit is further configured to write a parameter code for the operating parameter to one of the first and second registers responsive to a mode register write operation to a same mode register address associated with the first mode register.

8. The apparatus of claim 1 , further comprising a multiplexer coupled to the first register and the second register, wherein the control logic circuit is configured to control the multiplexer to provide to the control logic circuit one of the parameter codes for the operating parameter based on the parameter code stored for the control parameter.

9. An apparatus, comprising:
a memory configured to be set to a current operating condition, the memory including:
a mode register configured to store first and second parameter codes for a same operating parameter to set first and second operating conditions, respectively, for the operating parameter; and
a control logic circuit coupled to the first mode register and configured to set the current operating condition to the first operating condition using the first parameter code for the operating parameter based on a parameter code for a control parameter having a first logic value and set the current operating condition to the second operating condition using the second parameter code for the operating parameter based on the parameter code for the control parameter having a second logic value; and

a memory controller coupled to the memory and configured to write the first and second parameter codes for the operating parameter in the mode register and further configured to write the parameter code for the control parameter to set the current operation condition of the memory to the first or second operating conditions.

10. The apparatus of claim 9 wherein the memory and the memory controller are configured to perform training operations for the first and second operating conditions to determine the first and second parameter codes for the operating parameter.

11. The apparatus of claim 9 wherein the first and second operating conditions are related to operating conditions for a command bus coupled to the memory and the memory controller.

12. A method, comprising:
writing to a first register associated with a mode register a first parameter code for an operating parameter used to set a first memory operating condition;
writing to a second register associated with the mode register a second parameter code for the operating parameter used to set a second memory operating condition; and
writing a parameter code related to a control parameter to select between the first and second registers to be written responsive to a mode register write operation to the mode register address associated with the mode register.

13. The method of claim 12 wherein the mode register comprises a first mode register, and the method further comprises writing a parameter code to a register associated with a second mode register to select a stored parameter code for the operating parameter to set a current operation condition for a memory.

14. The method of claim 12 wherein writing to the first register associated with the mode register comprises writing the first parameter code to a mode register address associated with the mode register and wherein writing to the second register associated with the mode register comprises writing the second parameter code to the mode register address associated with the mode register.

15. The method of claim 12 wherein the mode register comprises a first mode register and the operating parameter comprises a first operating parameter, the method further comprises:
writing to a first register associated with a second mode register a first parameter code for a second operating parameter;
writing to a second register associated with the second mode register a second parameter code for the second operating parameter; and
selecting between the first parameter codes and the second parameter codes for the first and second operating parameters to set a current memory operating condition.

16. The method of claim 12 wherein the operating parameter comprises at least one of a burst length operating parameter, a preamble operating parameter, a precharge operating parameter, a postamble operating parameter, a latency parameter, a drive strength parameter, a data bus interface operating parameter, an on-die termination operating parameter, and a voltage reference operating parameter.

17. The method of claim 12 wherein the mode register comprises a first mode register and wherein writing to a first register associated with the first mode register a first parameter code for the operating parameter comprises:
writing a parameter code to a register associated with a second mode register, the parameter code indicative of writing a parameter code to the first register of the first mode register responsive to a mode register write operation to the first mode register instead of to the second register of the

Assignees

• Micron Technology Inc

Inventors

• Gans Dean D
• Skinner Daniel C

Classifications

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title