Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters

Patent metadata

Field	Value
Publication number	US-2021287724-A1
Application number	US-202117301531-A
Country	US
Kind code	A1
Filing date	Apr 6, 2021
Priority date	Apr 7, 2014
Publication date	Sep 16, 2021
Grant date	—

Abstract

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

First claim

What is claimed is:

1 . A method for controlling a memory device, the method comprising:
writing to a first register of a mode register a first parameter code for a burst length operating parameter used to set a first memory operating condition; writing to a second register of the mode register a second parameter code for the burst length operating parameter used to set a second memory operating condition; and writing a parameter code related to a control parameter to select between the first and second registers to be written.

2 . The method of claim 1 , wherein the mode register comprises a first mode register, and the method further comprises writing a parameter code to a register associated with a second mode register to select a stored parameter code for the burst length to set a current operating condition for a memory.

3 . The method of claim 1 , wherein writing to the first register comprises writing the first parameter code to a mode register address associated with the mode register and wherein writing to the second register associated with the mode register comprises writing the second parameter code to the mode register address associated with the mode register.

4 . The method of claim 1 , wherein the mode register comprises a first mode register and the method further comprises:
writing to a first register of a second mode register a first parameter code for an operating parameter; writing to a second register of the second mode register a second parameter code for the operating parameter; and selecting between the first parameter codes and the second parameter codes for the burst length operating parameter and the operating parameter to set a current memory operating condition.

5 . The method of claim 4 , wherein the operating parameter comprises at least one of a preamble operating parameter, a precharge operating parameter, a postamble operating parameter, a latency parameter, a drive strength parameter, a data bus interface operating parameter, an on-die termination operating parameter, and a voltage reference operating parameter.

6 . The method of claim 4 , wherein the first parameter codes and the second parameter codes for the burst length operating parameter and the operating parameter are selected simultaneously.

7 . The method of claim 1 , wherein the mode register comprises a first mode register and wherein writing to a first register of the first mode register a first parameter code for the burst length operating parameter comprises:
writing a parameter code to a register of a second mode register, the parameter code indicative of writing a parameter code to the first register of the first mode register responsive to a mode register write operation to the first mode register instead of to the second register of the first mode register; and commanding a mode register write operation to the first mode register to write the first parameter code.

8 . The method of claim 7 , wherein the parameter code associated with a first control parameter and the register comprises a first register, and the method further comprises writing a parameter code related to a second control parameter to a second register associated with the second mode register, the second parameter code indicative of using the first parameter code to set a current operation condition for a memory.

9 . A method for operating a memory device, comprising:
receiving a first memory command, the memory device comprising a first mode register comprising a first register and a second register, and a second mode register comprising a third register; and performing, responsive to the first memory command being a mode register write command for the first mode register:
writing a burst length operating parameter associated with the mode register write command for the first mode register to the first register when the third register is at a first write-selection value; or
writing the burst length operating parameter to the second register when the third register is at a second write-selection value.

10 . The method of claim 9 , further comprising setting one of a first memory operating condition or a second memory operating condition, the first memory operating condition based, at least in part, on the burst length operating parameter written to the first register and the second memory operating condition based, at least in part, on the burst length operating parameter written to the second register.

11 . The method of claim 10 , further comprising receiving a clock signal at a first frequency under the first memory operating condition and at a second frequency under the second memory operating condition.

12 . The method of claim 10 , wherein the burst length operating parameter written to the first register has a value different than the burst length operating parameter written to the second register.

13 . The method of claim 9 , wherein the first mode register is identified by a first mode register address and the second mode register is identified by a second mode register address.

14 . The method of claim 9 , further comprising:
receiving a second memory command; and performing, responsive to the second memory command being a mode register write command for the second mode register, writing data associated with the mode register write command for the second mode register to the third register to set the third register to one of the first and second write-selection values.

15 . The method of claim 14 , wherein the second mode register further comprises a fourth register and the method further comprises:
setting a first memory operating condition based, at least in part, on the burst length operating parameter written to first register when the fourth register is at a first condition-selection value and a second memory operating condition based, at least in part, on the burst length operating parameter written to second register when the fourth register is at a second condition-selection value.

16 . The method of claim 15 , wherein the first memory operating condition is associated with a first frequency of a clock signal and the second memory operating condition is associated with a second frequency of the clock signal.

17 . A method comprising:
storing in individual ones of a plurality of registers of a first mode register a corresponding plurality of values of a burst length operating parameter; and selecting a set point from a plurality of set points responsive to a value written to a second mode register, wherein the set point indicates a value of the plurality of values of the burst length operating parameter to be applied for operation of a memory.

18 . The method of claim 17 , further comprising storing individual ones of a plurality of registers of a third mode register a corresponding plurality of values of an operating parameter, wherein the set point indicates a value of the plurality of values of the operating parameter to be applied for the operation of the memory.

19 . The method of claim 18 , further comprising applying the value of the plurality of values of the burst length operating parameter and the value of the plurality of values of the operating parameter for the operation of the memory.

20 . The method of claim 17 , wherein the plurality of set points are associated with different frequencies of operation of the memory.

Assignees

• Micron Technology Inc

Inventors

• Gans Dean D
• Skinner Daniel C

Classifications

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title