Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters

Patent metadata

Field	Value
Publication number	US-10629245-B2
Application number	US-201916513431-A
Country	US
Kind code	B2
Filing date	Jul 16, 2019
Priority date	Apr 7, 2014
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

First claim

What is claimed is:

1. A method comprising:
storing in each of a plurality of registers a respective parameter associated with a different set point of a plurality of set points of an operating parameter; and
switching between the plurality of set points of the operating parameter responsive to a change in a value written to a mode register.

2. The method of claim 1 , wherein switching between the plurality of set points comprises selecting a set point of the plurality of set points of the operating parameter by writing a value associated with a desired set point of the plurality of set points to the mode register.

3. The method of claim 2 , further comprising selecting a register of the plurality of registers to write a parameter of the desired set point by writing the value associated with the desired set point to the register.

4. The method of claim 1 , further comprising storing in each of a second plurality of registers a respective second parameter associated with the different set point of the plurality of set points of a second operating parameter, wherein the plurality of set points of the operating parameter and the second operating parameter are switched between different set points of the plurality of set points simultaneously.

5. The method of claim 1 , wherein at least some of the registers of the plurality of registers have a same mode register address.

6. The method of claim 1 , wherein the at least one parameter includes a burst length.

7. A method comprising:
varying a first parameter of a signal provided to a memory;
evaluating a performance of the memory over variations of the first parameter;
selecting a value of the first parameter based on evaluating the performance of the memory; and
writing the value of the first parameter to a mode register to set a parameter code of a first set point.

8. The method of claim 7 , where in the signal is at least one of one of a command, an address, or a data signal.

9. The method of claim 7 , wherein the first parameter is at least one of a signal timing, a voltage range, or an on-die termination setting.

10. The method of claim 7 , wherein the signal is provided to the memory by a memory controller.

11. The method of claim 7 , further comprising holding a second parameter of the signal constant while the first parameter is varied.

12. The method of claim 11 , wherein the second parameter sets a parameter code of a second set point, wherein the first set point and the second set point define, at least in part, a first memory operating condition and a second memory operating condition, respectively.

13. The method of claim 7 , wherein the method is performed after power-up and initialization of the memory.

14. A method comprising:
providing a mode register write command to a memory by a memory controller, wherein the mode register write command causes the memory to write data associated with the mode register write command to a first register of the memory when a write-selection value stored in a second register of the memory is a first value, and
wherein the mode register write command causes the memory to write the data associated with the mode register write command to a third register of the memory when the write-selection value stored in the second register of the memory is a second value.

15. The method of claim 14 , wherein the first register and the third register are included in a first mode register, wherein the first mode register is identified by a first mode register address, and wherein the second register is included in a second mode register, wherein the second mode register is identified by a second mode register address.

16. The method of claim 14 , further comprising:
providing a second mode register write command to the memory by the memory controller, wherein the second mode register write command causes the memory to write second data associated with the second mode register write command to the second register to set the write selection value.

17. The method of claim 16 , wherein the second mode register write command further causes the memory to write third data associated with the second mode register write command to a fourth register to set an operating condition of the memory.

18. The method of claim 17 , wherein writing the first condition-selection value causes the memory to set a first memory operating condition and writing the second condition-selection value causes the memory to set a second memory operating condition.

19. The method of claim 17 , wherein the first register and the third register are included in a first mode register, the second register and the fourth register are included in a second mode register.

20. The method of claim 16 , wherein the first mode register write command and the second mode register write command are provided by the memory controller to the memory through a bus between the memory controller and the memory device.

Assignees

• Micron Technology Inc
• Micro Tech Inc

Inventors

• Gans Dean D
• Skinner Daniel C

Classifications

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title