Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters

Patent metadata

Field	Value
Publication number	US-10978115-B2
Application number	US-202016853917-A
Country	US
Kind code	B2
Filing date	Apr 21, 2020
Priority date	Apr 7, 2014
Publication date	Apr 13, 2021
Grant date	Apr 13, 2021

Abstract

Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

First claim

What is claimed is:

1. An apparatus comprising:
a memory comprising:
a plurality of registers, wherein individual ones of the plurality of registers are configured to store a respective parameter value of an operating parameter associated with a different set point of a plurality of set points; and
a mode register; and

a memory controller coupled to the memory and configured to write a value to the mode register, wherein the memory is configured to switch between the plurality of set points based on the value written to the mode register.

2. The apparatus of claim 1 , wherein the memory further comprises a second plurality of registers, wherein individual ones of the second plurality of registers are configured to store a respective second parameter value of a second operating parameter associated with the different set point of the plurality of set points.

3. The apparatus of claim 2 , wherein the memory is further configured to switch the plurality of set points of the operating parameter and the second operating parameter simultaneously.

4. The apparatus of claim 2 , wherein at the first plurality of registers and the second plurality of registers have a same mode register address.

5. The apparatus of claim 1 , wherein the memory further comprises a second mode register comprising the plurality of registers.

6. The apparatus of claim 1 , wherein the memory further comprises a control logic circuit coupled to the plurality of registers and the mode register, wherein the control logic circuit is configured to switch between the plurality of set points based on the value written to the mode register.

7. The apparatus of claim 1 , wherein the plurality of set points are associated with different operating frequencies of the memory.

8. The apparatus of claim 1 , further comprising a multiplexer coupled to the plurality of registers, wherein the multiplexer is configured to provide at least one of the respective parameter values, based at least in part, on the value written to the mode register.

9. The apparatus of claim 1 , further comprising a bus coupled to the memory and the memory controller, wherein the value is provided from the memory controller to the memory through the bus.

10. An apparatus comprising:
a memory comprising a plurality of registers, wherein individual ones of the plurality of registers are configured to store a respective parameter value associated with a different set point of a plurality of set points of an operating parameter; and
a memory controller coupled to the memory and configured to:
provide a training pattern to the memory;
evaluate a performance of the memory based on the training pattern; and
write a value of the respective parameter value associated with a first one of the plurality of set points of the operating parameter.

11. The apparatus of claim 10 , wherein the training pattern includes at least one of a command signal, an address signal, or data signal.

12. The apparatus of claim 10 , wherein the training pattern includes a signal and a parameter of the signal is varied in the training pattern.

13. The apparatus of claim 10 , wherein the parameter of the signal includes at least one of a signal timing, a voltage range, or an on-die termination setting.

14. The apparatus of claim 10 , wherein a second parameter of the signal is held constant in the training pattern.

15. The apparatus of claim 10 , further comprising a bus coupled to the memory and the memory controller, wherein the training pattern is provided from the memory controller to the memory through the bus.

16. The apparatus of claim 15 , wherein the bus is at least one of a command bus or an address bus.

17. The apparatus of claim 15 , wherein the bus is a data bus.

18. The apparatus of claim 10 , wherein the memory controller is further configured to:
provide a second training pattern to the memory;
evaluate the performance of the memory based on the second training pattern; and
write a value of the respective parameter value associated with a second one of the plurality of set points of the operating parameter.

19. The apparatus of claim 10 , wherein the memory further comprises a control logic circuit configured to set a current set point of the plurality of set points.

20. The apparatus of claim 19 , wherein the current set point is different than the first one of the plurality of set points.

Assignees

• Micron Technology Inc

Inventors

• Gans Dean D
• Skinner Daniel C

Classifications

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C7/1045 Primary

  Read-write mode select circuits · CPC title