Power semiconductor device having overvoltage protection and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11843045-B2
Application number	US-202017005642-A
Country	US
Kind code	B2
Filing date	Aug 28, 2020
Priority date	Mar 20, 2017
Publication date	Dec 12, 2023
Grant date	Dec 12, 2023

Abstract

A chip includes a semiconductor body coupled to a first and a second load terminal. The semiconductor body includes an active region including a plurality of breakthrough cells, each of the breakthrough cells includes: an insulation structure; a drift region; an anode region, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal; a first barrier region arranged in contact with each of the anode region and the insulation structure, where the first barrier region of the plurality of breakthrough cells forms a contiguous semiconductor layer; a second barrier region separating each of the anode region and at least a part of the first barrier region from the drift region; and a doped contact region arranged in contact with the second load terminal, where the drift region is positioned between the second barrier region and the doped contact region.

First claim

What is claimed is:

1. A method of processing an overvoltage protection power semiconductor chip, comprising:
providing a semiconductor body to be coupled to a first load terminal and a second load terminal of the overvoltage protection power semiconductor chip, the first load terminal to be arranged at a frontside and the second load terminal to be arranged at a backside of the overvoltage protection power semiconductor chip, and wherein the semiconductor body comprises each of an active region and an inactive edge region that surrounds the active region,
forming, in the active region a plurality of breakthrough cells, each breakthrough cell comprising an insulation structure arranged at the frontside and having a recess into which the first load terminal is to extend and to interface with the semiconductor body;
forming a drift region having dopants of a first conductivity type;
forming an anode region having dopants of a second conductivity type, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal;
forming a first barrier region having dopants of the second conductivity type at a lower dopant concentration than the anode region and arranged in contact with each of the anode region and the insulation structure, wherein the first barrier region forms a contiguous semiconductor layer throughout the plurality of breakthrough cells;
forming a second barrier region having dopants of the first conductivity type at a higher dopant concentration than the drift region and separating each of the anode region and at least a part of the first barrier region from the drift region; and
forming a doped contact region arranged in contact with the second load terminal, wherein the drift region is positioned between the second barrier region and the doped contact region.

2. The method of claim 1 , wherein at least one of forming the anode region, forming the first barrier region, and forming the second barrier region includes carrying out at least one implantation processing step.

3. The method of claim 2 , wherein at least one of the at least one implantation processing step is carried out with an ion energy of at least 1.5 MeV.

4. The method of claim 1 , further comprising:
forming a recombination zone that extends into at least the anode region by carrying out a self-aligned process using the insulation structure and the recess as a mask.

5. The method of claim 4 , wherein the self-aligned process includes a damage implantation processing step to form the recombination zone in alignment with the recess of the insulation structure.

6. The method of claim 4 , wherein the self-aligned process includes a diffusion processing step to form the recombination zone in alignment with the recess of the insulation structure.

7. The method of claim 4 , wherein forming the recombination zone includes introducing crystal defects into the semiconductor body by means of at least one of an implantation processing step and a diffusion processing step.

8. The method of claim 1 , wherein one or more breakthrough cells making up a portion of the plurality of breakthrough cells are configured to be in a conducting state only if a voltage applied at the first load terminal and the second load terminal exceeds an overvoltage threshold value.

9. The method of claim 1 , wherein a breakthrough cell of the plurality of breakthrough cells is configured to:
remain in a non-conducting state if a voltage between the first load terminal and the second load terminal is below a nominal chip blocking voltage; and
adopt to a conducting breakthrough state if the voltage between the first load terminal and the second load terminal is above the nominal chip blocking voltage.

10. The method of claim 9 , further comprising:
coupling the overvoltage protection power semiconductor chip to a power semiconductor transistor; and
configuring each of the plurality of breakthrough cells for a nominal chip blocking voltage that is determined in dependence of a nominal blocking voltage of the power semiconductor transistor.

11. The method of claim 1 , wherein each of the plurality of breakthrough cells comprises a recombination zone that extends into at least the anode region.

12. The method of claim 11 , wherein the recombination zone provides a locally decreased charge carrier lifetime.

13. The method of claim 1 , wherein:
the anode region and the first barrier region have a difference in a depth level such that the anode region extends deeper into the semiconductor body than the first barrier region forming a step, and
the step formed due to the difference in the depth level is covered by the second barrier region.

14. The method of claim 1 , wherein the plurality of breakthrough cells are arranged within the active region in accordance with a hexagonal tessellation pattern.

15. The method of claim 1 , wherein, in each of the plurality of breakthrough cells, the anode region, the first barrier region, and the second barrier region are arranged symmetrically with respect to a fictitious vertical axis traversing a respective breakthrough cell.

16. The method of claim 1 , wherein the doped contact region comprises a region of the second conductivity type.

17. The method of claim 1 , wherein a transition between the second load terminal and the doped contact region forms a Schottky contact.

18. The method of claim 1 , wherein the doped contact region comprises an emitter with dopants of the second conductivity type and a field stop region with dopants of the first conductivity type, the emitter being electrically connected to the second load terminal and the field stop region arranged between the drift region and the emitter.

19. The method of claim 1 , further comprising:
forming a diode arrangement arranged at the frontside of the semiconductor body and external to the semiconductor body, wherein the diode arrangement laterally overlaps with the inactive edge region and is connected to the first load terminal and to a further terminal.

20. The method of claim 1 , wherein the inactive edge region exhibits a greater breakdown voltage than each of the plurality of breakthrough cells.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Beninger-Bina Markus
• Basler Thomas
• Dainese Matteo
• Schulze Hans-Joachim

Classifications

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10D62/142

  Anode regions of thyristors or collector regions of gated bipolar-mode devices · CPC title

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title