Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-2016307993-A1
Application number	US-201615197821-A
Country	US
Kind code	A1
Filing date	Jun 30, 2016
Priority date	Jul 17, 2014
Publication date	Oct 20, 2016
Grant date	—

Abstract

A defective layer is formed by ion implanting argon for a p + anode layer from a front surface side of a base substrate. Here, the range of the argon is set to be shallower than the diffusion depth of the p + anode layer such that platinum atoms are localized in an electron entering region near a pn junction of the p + anode layer with an n − drift layer at a platinum diffusion step executed later. The platinum atoms in a platinum paste applied to the back surface of the base substrate are thereafter diffused in the p + anode layer to be localized on a cathode side of the defective layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type and disposed in the first semiconductor layer, the second semiconductor layer having an impurity concentration that is higher than that of the first semiconductor layer; and an argon-introduced region in the second semiconductor layer, including argon and disposed at a predetermined depth in the second semiconductor layer from a pn junction between the first semiconductor layer and the second semiconductor layer, wherein the semiconductor device includes platinum diffused in the first semiconductor layer and the second semiconductor layer, and the platinum has a platinum concentration distribution that has a maximal concentration in the argon-introduced region.

2 . The semiconductor device according to claim 1 , wherein the predetermined depth is a position at which a value obtained by integrating an impurity concentration of the second semiconductor layer from the pn junction toward the first surface is a critical integral concentration of the second semiconductor layer.

3 . The semiconductor device according to claim 1 , wherein a length from the pn junction toward the first surface side to the predetermined depth is a diffusion length of a first conductivity type carrier in the second semiconductor layer.

4 . A method of manufacturing a semiconductor device, comprising:
selectively forming a second semiconductor layer of a second conductivity type and having an impurity concentration that is higher than that of a first semiconductor layer of a first conductivity type, in a surface layer of a first surface of the first semiconductor layer; forming an argon-introduced region that includes argon, at a predetermined depth from a pn junction between the first semiconductor layer and the second semiconductor layer, by ion implanting argon from the first surface, such that the argon-introduced region has a thickness lass than that of the second semiconductor layer; and diffusing platinum into the second semiconductor layer from a second surface of the first semiconductor layer so as to localize the platinum in the argon introduced region.

5 . The method of manufacturing a semiconductor device, according to claim 4 , wherein diffusing the platinum into the second semiconductor layer from the first semiconductor layer comprises:
applying a platinum paste to the second surface of the first semiconductor layer; and heat-treating the platinum paste to diffuse the platinum into the second semiconductor layer.

6 . The method of manufacturing a semiconductor device, according to claim 5 , wherein the platinum paste is heat-treated at a temperature ranging from between 800 to 1,000 degrees C.

7 . The method of manufacturing a semiconductor device, according to claim 4 , wherein the argon-introduced region is formed at a depth that is one half of a depth of the second semiconductor layer from the first surface to a the pn junction.

8 . The method of manufacturing a semiconductor device, according to claim 4 , wherein forming the argon-introduced region includes adjusting a location of the argon-introduced region by adjusting an acceleration energy of the ion implanting of the argon.

9 . The method of manufacturing a semiconductor device, according to claim 8 , wherein the second semiconductor layer is disposed at a depth ranging from 1 to 10 μm from the first surface, and
the acceleration energy of the ion implanting of the argon ranges from 0.5 to 30 MeV.

10 . The method of manufacturing a semiconductor device, according to claim 8 , wherein the acceleration energy of the ion implanting of the argon is adjusted so that the range of the argon is positioned between the pn junction and a position at which a value obtained by integrating an impurity concentration of the second semiconductor layer from the pn junction toward the first surface is a critical integral concentration of the second semiconductor layer.

11 . The method of manufacturing a semiconductor device, according to claim 4 , wherein selectively forming the second semiconductor layer in the surface layer of the first surface of the first semiconductor layer comprises:
positioning a mask member on the first surface of the first semiconductor layer, the mask member having an opening therein; and diffusing a second conductivity type impurity onto the mask member to be ion-implanted through the opening of the mask member to form the second semiconductor layer.

12 . The method of manufacturing a semiconductor device, according to claim 11 , wherein the mask member has a thickness sufficient to block an ion-implantation of the argon.

13 . The method of manufacturing a semiconductor device, according to claim 11 , wherein the mask member comprises one of a resist film or an insulating film.

14 . The method of manufacturing a semiconductor device, according to claim 11 , wherein boron is ion-implanted as the second conductivity type impurity.

15 . The method of manufacturing a semiconductor device, according to claim 4 , wherein the second semiconductor layer is disposed as a guard ring layer constituting a voltage breakdown structure in a terminal region surrounding a periphery of one of an anode layer of a pn junction diode, an anode layer of a body diode of an insulated gate field effect transistor, a base layer of an insulated gate bipolar transistor, an anode layer of a diode portion of a reverse-conducting insulated gate bipolar transistor, and an active region.

16 . The semiconductor device according to claim 1 , wherein the second semiconductor layer is a p base layer of a metal oxide semiconductor field effect transistor (MOSFET).

17 . The semiconductor device according to claim 1 , wherein the semiconductor device is one of a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and a reverse-conducting insulated gate bipolar transistor (RC-IGBT).

18 . The semiconductor device according to claim 1 , wherein the second semiconductor layer is a p guard ring.

19 . The semiconductor device according to claim 1 , wherein the second semiconductor layer comprises a Schottky contact surface in which the first semiconductor layer forms a Schottky contact with a front surface electrode, and
a platinum concentration of the Schottky contact surface is lower than that of the argon introduced region.

20 . The method of manufacturing a semiconductor device, according to claim 4 , wherein the platinum is localized to have a platinum concentration distribution that has a maximal concentration in the argon introduced region.

Assignees

• Fuji Electric Co Ltd

Inventors

• Kuribayashi Hidenao
• Kitamura Shoji
• Onozawa Yuichi

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P32/18

  Diffusion lifetime killers · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title