Power semiconductor device

Patent metadata

Field	Value
Publication number	US-10355116-B2
Application number	US-201815926131-A
Country	US
Kind code	B2
Filing date	Mar 20, 2018
Priority date	Mar 20, 2017
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A power semiconductor device includes: a semiconductor body coupled to a first load terminal and a second load terminal, and includes: a first doped region of a second conductivity type electrically connected to the first load terminal; a recombination zone arranged at least within the first doped region; an emitter region of the second conductivity type electrically connected to the second load terminal; and a drift region of a first conductivity type arranged between the first doped region and the emitter region. The drift region and the first doped region enable the power semiconductor device to operate in: a conducting state during which a load current between the load terminals is conducted along a forward direction; in a forward blocking state during which a forward voltage applied between the load terminals is blocked; and in a reverse blocking state during which a reverse voltage applied between the terminals is blocked.

First claim

What is claimed is:

1. A power semiconductor device, comprising a semiconductor body coupled to a first load terminal and a second load terminal, and comprising:
a first doped region of a second conductivity type electrically connected to the first load terminal;
an emitter region of the second conductivity type electrically connected to the second load terminal;
a drift region of a first conductivity type and arranged between the first doped region and the emitter region; wherein the drift region and the first doped region enable the power semiconductor device to be operated in:
a conducting state during which a load current between the load terminals is conducted along a forward direction;
in a forward blocking state during which a forward voltage applied between the terminals is blocked; and in
a reverse blocking state during which a reverse voltage applied between the terminals is blocked; and
a recombination zone arranged at least within the first doped region.

2. The power semiconductor device of claim 1 , wherein:
a transition from the first doped region to the drift region forms a first diode,
a transition from the emitter region to the drift region forms a second diode, and
the first diode and the second diode are connected anti-serially with each other.

3. The power semiconductor device of claim 2 , wherein:
the first diode exhibits a first breakthrough voltage,
the second diode exhibits a second breakthrough voltage, and
the first breakthrough voltage is at least five times as great as the second breakthrough voltage.

4. The power semiconductor device of claim 1 , wherein each of the first load terminal, the first doped region, the recombination zone, the drift region, the emitter region, and the second load terminal exhibit a common lateral extension range.

5. The power semiconductor device of claim 1 , wherein the recombination zone is configured to reduce at least one of a lifetime and a mobility of charge carriers present within the recombination zone.

6. The power semiconductor device of claim 1 , wherein the recombination zone is laterally structured.

7. The power semiconductor device of claim 1 , further configured to induce a conduction channel within the first doped region for conduction of at least a part of the load current during the conducting state, wherein the induced conduction channel and the recombination zone are spatially separated from each other.

8. The power semiconductor device of claim 7 , wherein a minimum distance between the recombination zone and the induced conduction channel amounts to at least 50 nm.

9. The power semiconductor device of claim 1 , wherein the recombination zone exhibits a crystal defect concentration of at least 1000 times greater than a crystal defect concentration within the drift region.

10. The power semiconductor device of claim 1 , wherein the first doped region extends deeper into the semiconductor body than the recombination zone.

11. The power semiconductor device of claim 1 , wherein:
the first load terminal comprises a contact groove that interfaces with the first doped region, and
the recombination zone laterally overlaps with the contact groove and exhibits lateral dimensions within a range of 60% to 200% of the lateral dimensions of the contact groove.

12. The power semiconductor device of claim 1 , further comprising:
a plurality of cells each configured to operate in the conducting state, the forward blocking state, and the reverse blocking state.

13. The power semiconductor device of claim 1 , wherein the first doped region exhibits a first subsection and a second subsection, the first subsection interfacing with the first load terminal and having a higher dopant concentration than the second subsection, the second subsection interfacing with the drift region, wherein the recombination zone extends into each of the first subsection and the second subsection.

14. The power semiconductor device of claim 1 , wherein the power semiconductor device is a power semiconductor switch and further comprises:
a source region of the first conductivity type and electrically connected to the first load terminal, wherein the first doped region separates the source region from the drift region, wherein the recombination zone extends into the source region.

15. The power semiconductor device of claim 1 , further comprising:
an active region and an inactive edge region surrounding the active region,
wherein the active region comprises a plurality of cells, wherein the recombination zone is laterally structured in that only each of a share of the plurality of cells includes the recombination zone.

16. The power semiconductor device of claim 1 , further comprising:
an active region and an inactive edge region surrounding the active region,
wherein the active region comprises a plurality of cells, wherein the recombination zone is laterally structured in that the recombination zone is laterally structured within a horizontal cross-section of at least one of the plurality of the cells.

17. The power semiconductor device of claim 1 , further comprising:
a first barrier region of the second conductivity type at a lower dopant concentration than the first doped region and arranged in contact with both the first doped region and an insulation structure; and
a second barrier region of the first conductivity type at a higher dopant concentration than the drift region and separating both the first doped region and at least a part of the first barrier region from the drift region.

18. The power semiconductor device of claim 17 , further comprising:
an active region and an inactive edge region surrounding the active region, wherein at least one of the first barrier region and the second barrier region forms a contiguous semiconductor layer within the active region.

19. An integrated power semiconductor module comprising:
a power semiconductor transistor; and
an overvoltage protection power semiconductor chip comprising a semiconductor body coupled to a first load terminal and a second load terminal of the overvoltage protection power semiconductor chip, the first load terminal being arranged at a frontside and the second load terminal being arranged at a backside of the overvoltage protection power semiconductor chip, wherein the semiconductor body comprises an active region and an inactive edge region that surrounds the active region, and wherein the active region comprises a plurality of breakthrough cells;
wherein each breakthrough cell of the plurality of breakthrough cells comprises:
an insulation structure arranged at the frontside and having a recess into which the first load terminal extends and interfaces with the semiconductor body;
a drift region having dopants of a first conductivity type;
a first doped region implemented as an anode region and having dopants of a second conductivity type and being electrically connected to the first load terminal;
a first barrier region having dopants of the second conductivity type at a lower dopant concentration than a dopant concentration of the anode region and arranged in contact with each of the anode region and the insulation structure;
a second barrier region having dopants of the first conductivity type at a higher dopant concentration than a dopant concentration of the drift region and separating each of the anode region and at least a part of the first barrier region from the drift region; and
a doped contact region arranged in contact with the second load terminal, wherein the drift region

Assignees

• Infineon Technologies Austria Ag

Inventors

• Bina Markus
• Basler Thomas
• Dainese Matteo
• Schulze Hans-Joachim

Classifications

• H10W72/5473

  multiple bond wires connected to a common bond pad · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H01L27/0727

  Electricity · mapped topic

• H01L29/7393

  Electricity · mapped topic