Semiconductor device with enhancement and depletion FinFET cells

Patent metadata

Field	Value
Publication number	US-9659929-B2
Application number	US-201414529322-A
Country	US
Kind code	B2
Filing date	Oct 31, 2014
Priority date	Oct 31, 2014
Publication date	May 23, 2017
Grant date	May 23, 2017

Abstract

A semiconductor device includes enhancement FinFET cells and depletion FinFET cells. The enhancement FinFET cells include first gate structures separating first semiconductor fins. The depletion FinFET cells include second gate structures separating second semiconductor fins. Between the first and second gate structures a connection structure separates the first semiconductor fins from the second semiconductor fins. The connection structure has a specific conductance which is higher than a specific conductance in the second semiconductor fins.

First claim

What is claimed is:

1. A semiconductor device, comprising:
enhancement FinFET (fin field effect transistor) cells comprising first gate structures separating first semiconductor fins;
depletion FinFET cells comprising second gate structures separating second semiconductor fins; and
a connection structure arranged between the first and second gate structures and separating the first semiconductor fins from the second semiconductor fins, wherein a specific conductance of the connection structure is higher than in the second semiconductor fins.

2. The semiconductor device of claim 1 , wherein
the connection structure includes heavily doped semiconducting zones which are effective as drain zones for the enhancement FinFET cells and as source zones for the depletion FinFET cells.

3. The semiconductor device of claim 1 , wherein
a vertical extension of the connection structure is greater than a vertical extension of the first semiconductor fins.

4. The semiconductor device of claim 1 , wherein
the connection structure includes a semiconducting zone of the conductivity type of channel zones formed in the second semiconductor fins and an impurity concentration in the semiconducting zone is at least ten times as high as a mean net impurity concentration in the channel zones.

5. The semiconductor device of claim 1 , further comprising:
a metal contact structure directly adjoining the connection structure.

6. The semiconductor device of claim 1 , further comprising:
a transistor wiring electrically connecting a source zone of the enhancement FinFET cells with gate electrodes of the depletion FinFET cells.

7. The semiconductor device of claim 1 , further comprising:
a metal contact structure directly adjoining the connection structure;
further depletion FinFET cells comprising third gate structures arranged between third semiconductor fins;
a further connection structure arranged between the second and third gate structures, wherein a specific conductance of the further connection structure is higher than a specific conductance of the third semiconductor fins; and
a further transistor wiring electrically connecting the contact structure and the third gate structures.

8. The semiconductor device of claim 1 , further comprising:
a first Zener diode that comprises an anode electrically connected to a source zone of the enhancement FinFET cells and a cathode electrically connected with the connection structure.

9. The semiconductor device of claim 1 , wherein
longitudinal axes of the first gate structures and longitudinal axes of the second gate structures are parallel to a first lateral direction and a longitudinal axis of the connection structure extends in a second lateral direction tilted to the first lateral direction.

10. The semiconductor device of claim 1 , wherein
the connection structure includes contact zones of a conductivity type opposite to a conductivity type of channel zones formed in the second semiconductor fins, the contact zones directly adjoining portions of the channel zones that directly adjoin the second gate structures.

11. A semiconductor device, comprising:
enhancement FinFET (fin field effect transistor) cells comprising first gate structures arranged between first semiconductor fins;
first depletion FinFET cells comprising second gate structures arranged between second semiconductor fins and electrically connected with a source zone of the enhancement FinFET cells; and
second depletion FinFET cells comprising third gate structures arranged between third semiconductor fins and electrically connected with a source zone of the first depletion FinFET cells.

12. The semiconductor device of claim 11 , further comprising:
a first voltage limiting element that comprises a first electrode electrically connected to the source zone of the enhancement FinFET cells and a second electrode electrically connected with a source zone of the first depletion FinFET cells.

13. The semiconductor device of claim 12 , further comprising:
a second voltage limiting element that comprises a first electrode electrically connected to the source zone of the first depletion FinFET cells and a second electrode electrically connected with the source zone of the second depletion FinFET cells.

14. The semiconductor device of claim 11 , further comprising:
a connection structure arranged between the first and second gate structures, wherein a specific conductance of the connection structure is higher than a specific conductance in the second semiconductor fin.

15. The semiconductor device of claim 14 , further comprising:
a further connection structure arranged between the second and third gate structures, wherein a specific conductance of the further connection structure is higher than a specific conductance in the third semiconductor fin.

16. The semiconductor device of claim 14 , further comprising:
a metal contact structure directly adjoining the connection structure.

17. The semiconductor device of claim 16 , further comprising:
a transistor wiring electrically connecting the metal contact structure with third gate electrodes comprised in the third gate structures.

18. The semiconductor device of claim 11 , wherein
the first gate structures are arranged in first columns, the second gate structures in second columns and the third gate structures in third columns, wherein the second column is arranged between the first column and the third column.

19. The semiconductor device of claim 18 , further comprising:
a connection structure arranged between the first and the second column and a further connection structure between the second and the third columns.

Assignees

• Infineon Technologies Dresden Gmbh

Inventors

• Weis Rolf

Classifications

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H01L27/0886

  Electricity · mapped topic

• H01L27/0883 Primary

  Electricity · mapped topic

• H01L27/0629

  Electricity · mapped topic

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title