Semiconductor package structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11837526-B2
Application number	US-201916450657-A
Country	US
Kind code	B2
Filing date	Jun 24, 2019
Priority date	Jun 24, 2019
Publication date	Dec 5, 2023
Grant date	Dec 5, 2023

Abstract

A semiconductor structure includes a molding compound having a first surface and a second surface opposite to the first surface, a passive device component disposed in the molding compound, a via penetrating the molding compound from the first surface to the second surface, a first connection structure disposed over the first surface of the molding compound and electrically coupled to the passive device component, and a second connection structure disposed over the second surface of the molding compound. The first connection structure and the second connection structure are electrically coupled to each other by the via.

First claim

What is claimed is:

1. A semiconductor package structure comprising:
a first package structure comprising:
a passive device component comprising a semiconductor substrate;
a first molding compound having a first surface and a second surface opposite to the first surface;
a first connection structure disposed over the first surface;
a second connection structure disposed over the second surface;
a third connection structure disposed over the semiconductor substrate of the passive device component, wherein a width of the third connection structure and a width of the semiconductor substrate are the same;
a first via disposed in the first molding compound and electrically coupling the first connection structure to the second connection structure;
a first conductor disposed over the first connection structure; and
a second conductor disposed over the second connection structure;

a second package structure disposed over the first package structure, wherein the second package structure comprises:
a first die;
a second molding compound surrounding the first die, wherein the second molding compound has a third surface facing the first package structure and a fourth surface opposite to the third surface;
a fourth connection structure disposed over the third surface of the second molding compound; and
a third conductor disposed over the fourth connection structure and electrically coupled to the fourth connection structure;

a second via penetrating the second molding compound from the third surface to the fourth surface;
a fifth connection structure disposed over the fourth surface of the second molding compound; and
a fourth conductor disposed between the second molding compound and the fifth connection structure,
wherein the second package structure is electrically coupled to the first package structure through the first conductor, and the fifth connection structure is electrically coupled to the second via through the fourth conductor.

2. The semiconductor package structure of claim 1 , wherein a diameter of the third conductor is greater than diameters of the first conductor and the second conductor.

3. The semiconductor package structure of claim 1 , wherein the semiconductor substrate is in direct contact with the second connection structure.

4. The semiconductor package structure of claim 1 , wherein a width of the first package structure is less than a width of the second package structure.

5. The semiconductor package structure of claim 1 , wherein a width of the first connection structure, a width of the second connection structure, and a width of the first molding compound are the same.

6. The semiconductor package structure of claim 1 , wherein a width of the fourth connection structure and a width of the second molding compound are the same.

7. The semiconductor package structure of claim 1 , wherein a width of the fifth connection structure and a width of the second molding compound are the same.

8. A semiconductor package structure comprising:
a first package structure comprising:
a passive device component comprising a semiconductor substrate;
a first molding compound having a first surface and a second surface opposite to the first surface;
a first connection structure disposed over the first surface;
a second connection structure disposed over the second surface, wherein the semiconductor substrate is in direct contact with the second connection structure;
a third connection structure disposed over the semiconductor substrate of the passive device component, wherein a width of the third connection structure and a width of the semiconductor substrate are the same;
a via disposed in the first molding compound and electrically coupling the first connection structure to the second connection structure;
a first conductor disposed over the first connection structure; and
a second conductor disposed over the second connection structure; and

a second package structure comprising:
a die;
a second molding compound having a third surface and a fourth surface opposite to the third surface;
a fourth connection structure disposed over the third surface of the second molding compound; and
a third conductor disposed over and electrically coupled to the fourth connection structure,

wherein the second package structure is electrically coupled to the first package structure through the second conductor, and a width of the first package structure is less than a width of the second package structure.

9. The semiconductor package structure of claim 8 , wherein the third surface of the second molding compound faces the first package structure.

10. The semiconductor package structure of claim 8 , wherein a diameter of the third conductor is greater than diameters of the first conductor and the second conductor.

11. The semiconductor package structure of claim 8 , wherein the fourth connection structure is disposed between the die and the first package structure.

12. The semiconductor package structure of claim 8 , wherein the passive device component is electrically coupled to the first connection structure through the third connection structure.

13. The semiconductor package structure of claim 8 , wherein a width of the fourth connection structure and a width of the second molding compound are the same.

14. The semiconductor package structure of claim 8 , wherein the first package structure and the third conductor are disposed at a same level.

15. The semiconductor package structure of claim 8 , wherein the second package structure is electrically connected to the first package structure through the fourth connection structure.

16. A semiconductor package structure comprising:
a first package structure comprising:
a passive device component comprising a semiconductor substrate;
a first molding compound having a first surface and a second surface opposite to the first surface;
a first connection structure disposed over the first surface;
a second connection structure disposed over the second surface;
a third connection structure disposed over the semiconductor substrate of the passive device component, wherein a width of the third connection structure and a width of the semiconductor substrate are the same;
a first via disposed in the first molding compound and electrically coupling the first connection structure to the second connection structure;
a first conductor disposed over the first connection structure; and
a second conductor disposed over the second connection structure;

a second package structure comprising:
a first die;
a second molding compound having a third surface and a fourth surface opposite to the third surface;
a fourth connection structure disposed over the third surface of the second molding compound; and
a third conductor disposed over and electrically coupled to the fourth connection structure;

a third package structure electrically coupled to the second package structure, wherein the third package structure comprises:
a second die;
a fifth connection structure disposed over the second die; and
a fourth conductor disposed over and electrically coupled to the fifth connection structure; and

a second via disposed in the second molding compound, wherein the fourth connection structure is electrically coupled to the fifth connection structure through the second via,
wherein the second package structure is electrically coupled to the first package structure through the first conductor, and the third package structure is electrically coupled to the second package structure through the fourth conductor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Yang-Che
• Lin Chen-Hua
• Tseng Huang-Wen
• Liang Victor Chiang
• Liu Chwen-Ming

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W74/017

  Auxiliary layers for moulds, e.g. release layers or layers preventing residue · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title