Method and device for bonding of chips

Patent metadata

Field	Value
Publication number	US-11764198-B2
Application number	US-201716483077-A
Country	US
Kind code	B2
Filing date	Mar 2, 2017
Priority date	Mar 2, 2017
Publication date	Sep 19, 2023
Grant date	Sep 19, 2023

Abstract

A method and device for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.

First claim

What is claimed is:

1. A method for bonding a plurality of chips onto a first semiconductor substrate or onto further chips, wherein each chip is a rectangular part having been formed on a second semiconductor substrate, and wherein the method comprises:
separating the second semiconductor substrate into the plurality of chips;
positioning, by a bonding head, a hybrid bond surface of each of the plurality of separated chips onto the first semiconductor substrate or the further chips, said hybrid bond surface comprising an exposed dielectric surface region disposed in a first plane and an exposed electric surface region disposed in a second plane different from the first plane; and
bonding said hybrid bond surface onto the first semiconductor substrate or the further chips by a direct bond,
wherein bonding includes
the bond head applying the hybrid bond surface to the first semiconductor substrate or the further chips such that a bond wave of the direct bond spreads from a center of each hybrid bond surface toward an outer edge of the respective hybrid bond surface, wherein applying includes curving the bond head by accelerating the bond head toward the first semiconductor substrate or the further chips, and
the bond head releasing from fixation the hybrid bond surface.

2. The method according to claim 1 , wherein separating the second semiconductor substrate into the plurality of chips includes:
fixing the second semiconductor substrate onto a carrier, and
separating the second semiconductor substrate into the plurality of chips.

3. The method according to claim 2 , wherein the method includes:
cleaning the hybrid bond surface of the second semiconductor substrate prior to the fixing of the second semiconductor substrate onto the carrier and separating the second semiconductor substrate into the plurality of chips.

4. The method according to claim 2 , wherein the method includes:
cleaning the hybrid bond surfaces of the plurality of separated chips while removing the plurality of chips from the carrier and/or while transporting the plurality of chips to further positions.

5. The method according to claim 4 , wherein the further positions are bond positions.

6. The method according to claim 2 , wherein the method includes:
introducing grooves into the hybrid bond surface of the second semiconductor substrate before separating the second semiconductor substrate into the plurality of chips.

7. The method according to claim 2 , wherein the carrier is a tape.

8. The method according to claim 2 , wherein separating of the second semiconductor substrate into the plurality of chips includes use of a mechanical separating means.

9. The method according to claim 1 , further comprising attaching a curvable bond head to at least one chip of the plurality of separated chips, and using the curvable bond head to curve the hybrid bond surface of the at least one chip.

10. The method according to claim 1 , wherein the at least one chip of the plurality of separated chips comprises an integrated circuit.

11. A method for bonding a plurality of chips onto a first semiconductor substrate or onto further chips, wherein each chip is a rectangular part having been formed on a second semiconductor substrate, and wherein the method comprises:
separating the second semiconductor substrate into the plurality of chips;
positioning, by a bonding head, a hybrid bond surface of each of the plurality of separated chips onto the first semiconductor substrate or the further chips, said hybrid bond surface comprising an exposed dielectric surface region disposed in a first plane and an exposed electric surface region disposed in a second plane different from the first plane; and
bonding said hybrid bond surface onto the first semiconductor substrate or the further chips by a direct bond,
wherein bonding includes
the bond head applying the hybrid bond surface to the first semiconductor substrate or the further chips such that a bond wave of the direct bond spreads from a center of each hybrid bond surface toward an outer edge of the respective hybrid bond surface, wherein applying includes curving the bond head by accelerating the bond head toward the first semiconductor substrate or the further chips, and

the bond head releasing from fixation the hybrid bond surface, wherein the bond head applying the hybrid bond surface to the first semiconductor substrate or the further chips such that the bond wave of the direct bond spreads from the center of each hybrid bond surface toward the outer edge of the respective hybrid bond surface comprises:
generating an inertial force on the bond head due to acceleration of the bond head toward the first semiconductor substrate or the further chips;
opposing, in a central region of the bond head, the inertial force with a first force; and
opposing, in an outer region of the bond head, the inertial force with a second force that is different than the first force, whereby the bond head curves due to the inertial force, the first force and the second force.

Assignees

• Ev Group E Thallner Gmbh

Inventors

• Wimplinger Markus

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/07141

  Means for applying energy, e.g. ovens or lasers · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W46/301

  for alignment · CPC title