Chip-stacking apparatus

US2016190087A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2016190087-A1
Application numberUS-201414584889-A
CountryUS
Kind codeA1
Filing dateDec 29, 2014
Priority dateDec 29, 2014
Publication dateJun 30, 2016
Grant date

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  1. Title

    What the patent document calls the invention.

  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A chip-stacking apparatus for stacking a chip on a substrate is provided. The chip-stacking apparatus includes a substrate support configured to carry the substrate and a transport device configured to dispose a chip to the substrate. The transport device includes a bond head including a bond base and an attaching element disposed on the bond base and configured to allow the chip to be attached thereon. The center area of the attaching element is higher than an edge area of the attaching element relative to the bond base.

First claim

Opening claim text (preview).

What is claimed is: 1 . A chip-stacking apparatus for stacking a chip on a substrate, comprising: a substrate support configured to carry the substrate, and a transport device configured to dispose a chip onto the substrate, wherein the transport device comprises a bond head comprising: a bond base; and an attaching element, disposed on the bond base, configured to allow the chip to be attached thereon, wherein a center area of the attaching element is higher than an edge area of the attaching element relative to the bond base. 2 . The chip-stacking apparatus as claimed in claim 1 , wherein the attaching element has a warped surface, and the chip is warped along the attaching surface when the chip is attached to the attaching element. 3 . The chip-stacking apparatus as claimed in claim 2 , wherein the attaching element comprises an edge wall and a center wall disposed on the bond base, the edge wall is around the center wall, wherein the top surfaces of the edge wall and the center wall are a part of the warped surface. 4 . The chip-stacking apparatus as claimed in claim 1 , wherein the transport device further comprises a vacuum pump coupled with the bond head, and the bond head generates a suction force to the chip by the vacuum pump. 5 . The chip-stacking apparatus as claimed in claim 4 , wherein the attaching element has a vacuum hole located at the center area, and the bond head attracts the chip using the suction force via the vacuum hole. 6 . The chip-stacking apparatus as claimed in claim 4 , wherein the attaching element has a plurality of vacuum holes located at the edge area, and the bond head attracts the chip using the suction force via the vacuum holes. 7 . The chip-stacking apparatus as claimed in claim 1 , wherein the transport device further comprises a transport mechanism configured to move the bond head with the chip toward the substrate. 8 . A chip-stacking apparatus for stacking a chip on a substrate, comprising: a substrate support configured to carry the substrate; a transport device configured to dispose a chip onto the substrate, wherein the transport device comprises a bond head comprising: a bond base; and an attaching element, comprising an edge area surrounding a center area and a plurality of vacuum holes located at the edge area, disposed on the bond base and configured to allow the chip to be attached thereon; and a vacuum pump, coupled with the bond head, configure to make the bond head having a suction force via the vacuum holes, wherein the suction force of the bond head at the edge area is stronger than that of the center area. 9 . The chip-stacking apparatus as claimed in claim 8 , wherein the attaching element comprises an attaching surface configured to allow the chip to be attached thereon, and the attaching surface is a flat surface. 10 . The chip-stacking apparatus as claimed in claim 9 , wherein the center of the chip is separated from the attaching surface when the edge of the chip is attached to the attaching surface. 11 . The chip-stacking apparatus as claimed in claim 8 , wherein the transport device further comprises a pushing element disposed on the attaching element and located at a center area of the attaching element, wherein the pushing element is movable for pushing the center area of the chip. 12 . The chip-stacking apparatus as claimed in claim 8 , wherein the attaching element comprises an attaching surface, and the attaching surface is a warped surface which allows the chip warped along the warped surface when the chip is attached on the attaching element. 13 . The chip-stacking apparatus as claimed in claim 8 , wherein the transport device further comprises a transport mechanism configured to move the bond head with the chip toward the substrate. 14 . A chip-stacking apparatus, comprising: a first cleaning device configured to clean a substrate; a second cleaning device configured to clean a chip; a chip-stacking device configured to stack the chip on the substrate; and an alignment device configured to checking an offset between the chip and the substrate when the chip is stacked on the substrate. 15 . The chip-stacking apparatus as claimed in claim 14 , wherein the first cleaning device further comprises a first dry-cleaning device configured to clean the substrate using plasma or gas, and a first wet-cleaning device configured to clean the substrate using liquid. 16 . The chip-stacking apparatus as claimed in claim 14 , wherein the second cleaning device further comprises a second dry-cleaning device configured to clean the chip by plasma or gas and a second wet-cleaning device configured to clean the chip using liquid. 17 . The chip-stacking apparatus as claimed in claim 14 , wherein the chip-stacking device further comprises a transport device configured to transfer the chip onto the substrate, wherein the transport device comprises a bond head comprising: a bond base; and an attaching element, disposed on the bond base, configured to allow the chip to be attached thereon. 18 . The chip-stacking apparatus as claimed in claim 17 , wherein the attaching element has a warped surface, and the chip is warped along the attaching surface when the chip is attached to the attaching element. 19 . The chip-stacking apparatus as claimed in claim 17 , further comprising a chip-cleaning device configured to clean the chip when the chip is attached to the bond head. 20 . The chip-stacking apparatus as claimed in claim 14 , further comprising a debonding device configured to separate the chip from the substrate if the chip is not aligned with the substrate.

Assignees

Inventors

Classifications

  • using active alignment, e.g. detecting marks and correcting position · CPC title

  • Means for aligning · CPC title

  • Means for moving chips, wafers or other parts, e.g. conveyor belts · CPC title

  • Means for applying energy, e.g. ovens or lasers · CPC title

  • Means for cleaning, e.g. brushes · CPC title

Patent family

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Frequently asked questions

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What does patent US2016190087A1 cover?
A chip-stacking apparatus for stacking a chip on a substrate is provided. The chip-stacking apparatus includes a substrate support configured to carry the substrate and a transport device configured to dispose a chip to the substrate. The transport device includes a bond head including a bond base and an attaching element disposed on the bond base and configured to allow the chip to be attached…
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W72/0711. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jun 30 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).