Stacked device, stacked structure, and method of manufacturing stacked device

Patent metadata

Field	Value
Publication number	US-2019363068-A1
Application number	US-201916534464-A
Country	US
Kind code	A1
Filing date	Aug 7, 2019
Priority date	Mar 21, 2017
Publication date	Nov 28, 2019
Grant date	—

Abstract

A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

First claim

What is claimed is:

1 . A stacked device comprising:
a stacked structure in which a plurality of semiconductors are electrically connected to each other, wherein the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

2 . The stacked device according to claim 1 ,
wherein the semiconductor includes an insulating layer on the surface, and a height from the surface of the semiconductor to a surface of the terminal is higher than a height from the surface of the semiconductor to a surface of the insulating layer by 200 nm to 1 μm.

3 . The stacked device according to claim 1 ,
wherein the plurality of terminals are directly bonded to each other.

4 . The stacked device according to claim 1 ,
wherein the plurality of terminals are bonded through an anisotropic conductive member having a conductive path that extends in a stacking direction, and the conductive path has a diameter of 100 nm or less.

5 . The stacked device according to claim 4 ,
wherein the anisotropic conductive member includes an insulating substrate and plural of the conductive paths that penetrate the insulating substrate in a thickness direction and are provided in a state where the conductive paths are electrically insulated from each other.

6 . The stacked device according to claim 1 , further comprising:
an interposer.

7 . A stacked structure comprising:
a plurality of semiconductors that are electrically connected to each other, wherein the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminals that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.

8 . The stacked structure according to claim 7 ,
wherein the semiconductor includes an insulating layer on the surface, and a height from the surface of the semiconductor to a surface of the terminal is higher than a height from the surface of the semiconductor to a surface of the insulating layer by 200 nm to 1 μm.

9 . The stacked structure according to claim 7 ,
wherein the plurality of terminals are directly bonded to each other.

10 . The stacked structure according to claim 7 ,
wherein the plurality of terminals are bonded through an anisotropic conductive member having a conductive path that extends in a stacking direction, and the conductive path has a diameter of 100 nm or less.

11 . The stacked structure according to claim 10 ,
wherein the anisotropic conductive member includes an insulating substrate and plural of the conductive paths that penetrate the insulating substrate in a thickness direction and are provided in a state where the conductive paths are electrically insulated from each other.

12 . The stacked structure according to claim 7 , further comprising:
an interposer.

13 . A method of manufacturing the stacked device according to claim 1 , the method comprising:
temporarily bonding the respective semiconductors; and collectively bonding all the semiconductors.

Assignees

• Fujifilm Corp

Inventors

• Hotta Yoshinori

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W72/0198

  batch processes · CPC title