Local isolation of source/drain for reducing parasitic capacitance in vertical field effect transistors

Patent metadata

Field	Value
Publication number	US-11742246-B2
Application number	US-202117502210-A
Country	US
Kind code	B2
Filing date	Oct 15, 2021
Priority date	Aug 1, 2019
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.

First claim

What is claimed is:

1. A method for forming a semiconductor structure comprising a plurality of vertical field effect transistors, the method comprising at least:
forming a plurality of source/drain layers each in contact with at least one semiconductor fin of a plurality of semiconductor fins and each isolated from one another by an isolation trench, wherein each isolation trench comprises an isolation material;
recessing the isolation material in each isolation trench below a top surface of the plurality of source/drain layers, wherein the recessing exposes sidewalls of the plurality of source/drain layers;
forming a spacer layer in contact with at least a top surface and the sidewalls of each source/drain layer of the plurality of source/drain layers;
removing one or more portions of the spacer layer to expose an end portion of each source/drain layer of the plurality of source/drain layers underlying a region where a gate structure is to be subsequently formed;
recessing the exposed one or more end portions, the recessing forming a notched region within each source/drain layer of the plurality of source/drain layers; and
forming a dielectric layer within each notched region.

2. The method of claim 1 , wherein forming the spacer layer pinches off each isolation trench.

3. The method of claim 1 , wherein forming each of dielectric layers comprises:
forming the dielectric layer in contact with the source/drain layer and a portion of the spacer layer.

4. The method of claim 3 , wherein forming the dielectric layer on the portion of the spacer layer comprises:
forming the dielectric layer in contact with a sidewall and a top surface of the portion of the spacer layer.

5. The method of claim 1 , wherein the dielectric layer isolates the end portion of the source/drain layer from the gate structure and a portion of the spacer layer.

6. The method of claim 1 , wherein prior to removing the one or more portions of the spacer layer, the method comprises:
forming one or more oxide layers over horizontal portions of the spacer layer except for the one or more portions of the spacer layer, wherein the one or more oxide layers protect underlying portions of the spacer layer during removal of the one or more portions of the spacer layer for exposing the end portion of each source/drain layer of the plurality of source/drain layers.

7. The method of claim 1 , wherein after each dielectric layer has been formed within each notched region, the method further comprises:
removing portions of the spacer layer from vertical surfaces of each source/drain layer of the plurality of source/drain layers and vertical surfaces of the plurality of semiconductor fins.

8. The method of claim 7 , further comprising:
forming a plurality of metal gate structures, each metal gate structure being formed in contact with sidewalls of at least one semiconductor fin of the plurality of semiconductor fins, one of the dielectric layers, and a portion of the spacer layer;
forming a plurality of additional spacer layers, each additional spacer layer being formed above one of the spacer layers and in contact with a top surface of one of the metal gate structures of the plurality of metal gate structures, and further in contact with sidewalls of at least one semiconductor fin of the plurality of semiconductor fins; and
forming a plurality of additional source/drain layers above one of the source/drain layers of the plurality of source/drain layers, each additional source/drain layer being formed in contact with a top surface of one of the additional spacer layers of the plurality of additional spacer layers and further in contact with a top surface of at least one semiconductor fin of the plurality of semiconductor fins.

9. A vertical field effect transistor structure comprising:
a source/drain layer in contact with at least one semiconductor fin, wherein an edge portion of the source/drain layer comprises a notched region comprising a dielectric material;
a spacer layer comprising a first portion in contact with at least a top surface of the source/drain layer and a second portion in contact with the dielectric material; and
a gate structure in contact with at least the first portion of the spacer layer and the dielectric material,
wherein the dielectric material within the notched region contacts a vertical sidewall of the source/drain layer and a top surface of a portion of the source/drain layer in contact with an isolation region.

10. The vertical field effect transistor structure of claim 9 , wherein the dielectric layer isolates at least a portion of the source/drain layer from the gate structure and the spacer layer.

11. The vertical field effect transistor structure of claim 9 , wherein the dielectric layer contacts a sidewall and a top surface of the portion of the spacer layer.

12. The vertical field effect transistor structure of claim 9 , further comprising:
an additional spacer layer formed above the spacer layer and in contact with the at least one semiconductor fin and an additional source/drain layer formed above the source/drain layer.

13. The vertical field effect transistor structure of claim 9 , further comprising:
an additional source/drain layer formed in contact with a top surface of the at least one semiconductor fin and an additional spacer layer.

14. A vertical field effect transistor structure comprising:
a source/drain layer in contact with at least one semiconductor fin, wherein an edge portion of the source/drain layer comprises a notched region comprising a dielectric material in contact with the edge portion;
a spacer layer in contact with the source/drain layer and the dielectric material; and
a gate structure in contact with at least a portion of the spacer layer and the dielectric material,
wherein a first portion of the dielectric material comprises a top surface that is coplanar with a top surface of the source/drain layer, and wherein a second portion of the dielectric material extends over and contacts a portion of the spacer layer formed over and in contact with an isolation region.

15. The vertical field effect transistor structure of claim 14 , wherein the dielectric layer isolates at least a portion of the source/drain layer from the gate structure and the spacer layer.

16. The vertical field effect transistor structure of claim 14 , wherein the dielectric layer contacts a sidewall and a top surface of the portion of the spacer layer.

17. The vertical field effect transistor structure of claim 14 , further comprising:
an additional spacer layer formed above the spacer layer and in contact with the at least one semiconductor fin and an additional source/drain layer formed above the source/drain layer.

18. The vertical field effect transistor structure of claim 14 , further comprising:
an additional source/drain layer formed in contact with a top surface of the at least one semiconductor fin and an additional spacer layer.

19. The vertical field effect transistor structure of claim 14 , wherein the dielectric material comprise an air gap.

20. The vertical field effect transistor structure of claim 14 , wherein the spacer layer comprises a first portion in contact with at least a top surface of the source/drain layer and a second portion in contact with the dielectric material.

Assignees

• IBM

Inventors

• Xie Ruilong
• Jagannathan Hemanth
• Waskiewicz Christopher J
• Reznicek Alexander

Classifications

• H10D84/837

  comprising vertical IGFETs · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title