Uniform bottom spacers in vertical field effect transistors

Patent metadata

Field	Value
Publication number	US-10157798-B1
Application number	US-201715808467-A
Country	US
Kind code	B1
Filing date	Nov 9, 2017
Priority date	Nov 9, 2017
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A method for forming a semiconductor device includes forming a semiconductor fin over a surface of a substrate and forming sacrificial spacers on first and second sides of the semiconductor fin. The first side opposes the second side. The method includes recessing the surface to expose second and third surfaces, recessing the second surface to form a first cavity between the sacrificial spacers and the substrate on the first side, and recessing the third surface to form a second cavity between the sacrificial spacers and the substrate on the second side. The method includes forming a first bottom spacer in the first cavity and forming a second bottom spacer in the second cavity. A thickness of the first bottom spacer in a direction between the sacrificial spacers and the substrate is substantially equal to a thickness of the second bottom spacer in the same direction.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a semiconductor fin over a first surface of a substrate;
forming sacrificial spacers on a first side of the semiconductor fin and a second side of the semiconductor fin, the first side of the semiconductor fin opposing the second side of the semiconductor fin;
recessing the first surface of the substrate to expose a second surface of the substrate and a third surface of the substrate;
recessing the second surface of the substrate to form a first cavity between a first portion of the sacrificial spacers and the substrate on the first side of the semiconductor fin;
recessing the third surface of the substrate to form a second cavity between a second portion of the sacrificial spacers and the substrate on the second side of the semiconductor fin;
forming a first bottom spacer in the first cavity; and
forming a second bottom spacer in the second cavity;
wherein a thickness of the first bottom spacer in a direction between the first portion of the sacrificial spacers and the substrate is substantially equal to a thickness of the second bottom spacer in a direction between the second portion of the sacrificial spacers and the substrate.

2. The method of claim 1 , wherein each of the first bottom spacer and the second bottom spacer comprises silicon nitride.

3. The method of claim 1 further comprising removing the sacrificial spacers.

4. The method of claim 3 further comprising forming a conductive gate contacting the semiconductor fin.

5. The method of claim 1 , wherein each of the second surface of the substrate and the third surface of the substrate is substantially perpendicular to the first surface of the substrate.

6. The method of claim 1 , wherein an underlying surface of the substrate is exposed after recessing the second surface of the substrate.

7. The method of claim 6 , wherein the underlying surface of the substrate is substantially parallel to the first surface of the substrate.

8. The method of claim 7 further comprising forming a third bottom spacer on the underlying surface of the substrate.

9. The method of claim 8 , wherein the thickness of the first bottom spacer is less than a thickness of the third bottom spacer in the direction between the first portion of the sacrificial spacers and the substrate.

10. The method of claim 8 , wherein the thickness of the first bottom spacer is greater than a thickness of the third bottom spacer in the direction between the first portion of the sacrificial spacers and the substrate.

11. The method of claim 8 , wherein the third bottom spacer comprises silicon oxide, silicon nitride, or silicon oxynitride.

12. The method of claim 1 , wherein a width of the first bottom spacer in a direction orthogonal to the between the first portion of the sacrificial spacers and the substrate is substantially equal to a width of the first portion of the sacrificial spacers on the first side of the semiconductor fin in the direction orthogonal to the direction between the first portion of the sacrificial spacers and the substrate.

13. The method of claim 1 , wherein a width of the first bottom spacer in a direction orthogonal to the direction between the first portion of the sacrificial spacers and the substrate is less than a width of the first portion of the sacrificial spacers on the first side of the semiconductor fin in the direction orthogonal to the direction between the first portion of the sacrificial spacers and the substrate.

Assignees

• IBM

Inventors

• Chi Cheng
• Sung Min Gyu
• Xie Ruilong
• Yamashita Tenko

Classifications

• H01L29/66666

  Electricity · mapped topic

• H01L21/823487 Primary

  Electricity · mapped topic

• H01L21/823468

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H10D84/8316

  the IGFETs characterised by having gate sidewall spacers specially adapted for integration · CPC title