Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain

Patent metadata

Field	Value
Publication number	US-9899515-B1
Application number	US-201615339072-A
Country	US
Kind code	B1
Filing date	Oct 31, 2016
Priority date	Oct 31, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

First claim

What is claimed is:

1. A method of fabricating a vertical fin field effect transistor with a merged top source/drain, comprising:
forming a source/drain layer at the surface of a substrate;
forming a plurality of vertical fins on the source/drain layer;
forming protective spacers on each of the plurality of vertical fins;
forming a sacrificial plug between two protective spacers;
forming a filler layer on the protective spacers not in contact with the sacrificial plug;
selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers;
extending the isolation region trench through the source/drain layer into the substrate; and
forming a dummy layer in the isolation region trench.

2. The method of claim 1 , further comprising patterning the dummy layer and forming at least two additional isolation region trenches in the source/drain layer and substrate.

3. The method of claim 2 , further comprising removing the dummy layer and forming a trench fill layer in the at least three isolation region trenches.

4. The method of claim 3 , further comprising etching back the trench fill layer to form a plurality of shallow trench isolation regions, and forming a gate structure on each of the plurality of vertical fins.

5. The method of claim 4 , further comprising forming a top source/drain on each of the plurality of vertical fins having a predetermined size, where the predetermined size is sufficient for at least two top source/drains to coalesce into the merged top source/drain.

6. The method of claim 5 , wherein the distance between at least two adjacent vertical fins of the plurality of vertical fins is in the range of about 10 nm to about 40 nm, and the predetermined size of the at least two top source/drains is greater than the distance between the at least two adjacent vertical fins.

7. The method of claim 6 , wherein the distance between adjacent pairs of vertical fins of the plurality of vertical fins other than the at least two adjacent vertical fins is in the range of about 30 nm to about 100 nm, and the predetermined size of the top source/drains other than the at least two top source/drains is less than the distance between the adjacent pairs of vertical fins of the plurality of vertical fins other than the at least two adjacent vertical fins.

8. A method of fabricating two vertical fin field effect transistors electrically coupled through a merged top source/drain, comprising:
forming a source/drain layer on a substrate;
forming at least four vertical fins on the source/drain layer;
forming a protective spacer on the sidewalls of each of the at least four vertical fins;
forming an isolation region through the source/drain layer by forming an isolation region trench between two facing protective spacers on two adjacent vertical fins, forming a dummy layer in the isolation region trench, removing the dummy layer, and forming a trench fill layer in the isolation region trench to separate the source/drain layer into a first bottom source/drain and a second bottom source/drain, wherein at least two of the least four vertical fins are on the first bottom source/drain, and at least two of the at least four vertical fins are on the second bottom source/drain; and
forming a top source/drain on each of the at least four vertical fins, wherein the top source/drains are formed to a size that is sufficient for at least two top source/drains to coalesce into the merged top source/drain.

9. The method of claim 8 , wherein the at least two vertical fins on the first bottom source/drain are separated by a distance in the range of about 30 nm to about 100 nm, and the at least two vertical fins on the second bottom source/drain are separated by a distance in the range of about 30 nm to about 100 nm.

10. The method of claim 8 , wherein one vertical fin on the first bottom source/drain is separated from an adjacent vertical fin on the second bottom source/drain by a distance in the range of about 10 nm to about 40 nm.

11. The method of claim 8 , wherein the top source/drains are epitaxially grown on each of the at least four vertical fins.

12. The method of claim 11 , further comprising forming a gate structure on each of the at least four vertical fins.

13. The method of claim 12 , further comprising forming electrical contacts to at least one top source/drain on the first bottom source/drain that is not the merged top source/drain, and forming electrical contacts to at least one top source/drain on the second bottom source/drain that is not the merged top source/drain.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Miao Xin
• Xu Wenyu
• Zhang Chen

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/837

  comprising vertical IGFETs · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/0151

  Manufacturing their isolation regions · CPC title