Vertical transistor structure with reduced parasitic gate capacitance

Patent metadata

Field	Value
Publication number	US-9780194-B1
Application number	US-201615082131-A
Country	US
Kind code	B1
Filing date	Mar 28, 2016
Priority date	Mar 28, 2016
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A method of forming a gate spacer in a vertical transistor includes depositing a gate spacer layer on a source layer and a sacrificial gate material on the gate spacer layer; etching a trench through the sacrificial gate material and the gate spacer and forming an epitaxial channel within the trench; removing a portion of the sacrificial gate material to expose a portion of the gate spacer layer and leave the sacrificial gate material arranged on sidewalls of the channel; depositing an ultra-low-k spacer material on the gate spacer layer such that the ultra-low-k spacer material contacts a sidewall of the sacrificial gate material; and removing remaining portions of the sacrificial gate material and replacing the sacrificial gate material with a metal gate.

First claim

What is claimed is:

1. A vertical transistor, comprising:
a doped source layer arranged on a substrate;
a gate spacer layer arranged directly on the doped source layer;
an ultra-low-k spacer layer arranged directly on the gate spacer layer;
a channel extending vertically from the doped source layer to a drain, the gate spacer layer directly contacting two sides of the channel;
a recess formed within the ultra-low-k spacer layer that is adjacent to the channel; and
a gate arranged on the doped source and in the recess within the ultra-low-k spacer layer, a bottom surface of the gate contacting the gate spacer layer, and sidewalls of the gate contacting the ultra-low-k spacer layer.

2. The vertical transistor of claim 1 , wherein the doped source layer comprises a dopant incorporated into the substrate.

3. The vertical transistor of claim 2 , further comprising a counter-doped layer arranged between the substrate and the doped source layer, the counter-doped layer comprising a dopant that is different than the dopant of the doped source layer.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Cheng Kangguo
• Hashemi Pouya
• Reznicek Alexander

Classifications

• H01L29/7827

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L29/6656 Primary

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/4966

  Electricity · mapped topic