Nonvolatile memory device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11715712-B2
Application number	US-202117323076-A
Country	US
Kind code	B2
Filing date	May 18, 2021
Priority date	Oct 5, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A nonvolatile memory device includes an upper insulating layer. A first substrate is on the upper insulating layer. An upper interlayer insulating layer is on the first substrate. A plurality of word lines is stacked on the first substrate in a first direction and extends through a partial portion of the upper interlayer insulating layer. A lower interlayer insulating layer is on the upper interlayer insulating layer. A second substrate is on the lower interlayer insulating layer. A lower insulating layer is on the second substrate. A dummy pattern is composed of dummy material. The dummy pattern is disposed in a trench formed in at least one of the first and second substrates. The trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
an upper insulating layer;
a first substrate on the upper insulating layer;
an upper interlayer insulating layer on the first substrate;
a plurality of word lines stacked on the first substrate in a first direction and extending through a partial portion of the upper interlayer insulating layer;
a lower interlayer insulating layer on the upper interlayer insulating layer;
a second substrate on the lower interlayer insulating layer;
a lower insulating layer on the second substrate; and
a dummy pattern composed of dummy material, the dummy pattern is disposed in a trench formed in at least one of the first and second substrates, wherein the trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate, the trench extending solely within the at least one of the first and second substrates.

2. The nonvolatile memory device of claim 1 , wherein:
the trench is formed in both the first substrate and the second substrate; and
the dummy material of the dummy pattern fills the trench formed in both the first substrate and the second substrate.

3. The nonvolatile memory device of claim 1 , wherein:
a thinning process is performed on at least one of the first substrate and the second substrate; and
the trench is formed in the at least one of the first substrate and the second substrate which has been subjected to the thinning process.

4. The nonvolatile memory device of claim 3 , wherein the thinning process includes a chemical mechanical polishing (CMP) process.

5. The nonvolatile memory device of claim 3 , wherein the thinning process includes a grinding process.

6. The nonvolatile memory device of claim 1 , wherein the dummy material includes a conductive material.

7. The nonvolatile memory device of claim 1 , wherein the dummy material includes an insulating material.

8. The nonvolatile memory device of claim 1 , wherein the dummy pattern extends in a same direction that the plurality of word lines extend.

9. The nonvolatile memory device of claim 1 , wherein the dummy pattern extends in a direction that intersects a direction in which the plurality of word lines extend.

10. The nonvolatile memory device of claim 1 , wherein the dummy pattern extends in a direction in which the plurality of word lines extend and a direction that intersects the direction in which the plurality of word lines extend.

11. A nonvolatile memory device comprising:
an upper insulating layer;
a first substrate on the upper insulating layer;
an upper interlayer insulating layer on the first substrate;
a plurality of word lines stacked on the first substrate in a first direction and extending through a partial portion of the upper interlayer insulating layer;
a channel structure extending in the first direction to penetrate the plurality of word lines and a partial portion of the upper interlayer insulating layer;
a lower interlayer insulating layer on the upper interlayer insulating layer;
a second substrate on the lower interlayer insulating layer;
a lower insulating layer on the second substrate; and
a dummy pattern composed of dummy material, the dummy pattern is disposed in a trench formed in at least one of the first and second substrates, wherein the trench is formed on at least one of a surface where the upper insulating layer meets the first substrate, and a surface where the lower insulating layer meets the second substrate, the trench extending solely within the at least one of the first and second substrates.

12. The nonvolatile memory device of claim 11 , wherein:
the trench is formed in both the first substrate and the second substrate; and
the dummy material of the dummy pattern fills the trench formed in both the first substrate and the second substrate.

13. The nonvolatile memory device of claim 11 , wherein:
a thinning process is performed on at least one of the first substrate and the second substrate; and
the trench is formed in the at least one of the first substrate and the second substrate which has been subjected to the thinning process.

14. The nonvolatile memory device of claim 11 , wherein the dummy material includes a conductive material.

15. The nonvolatile memory device of claim 11 , wherein the dummy material includes an insulating material.

16. The nonvolatile memory device of claim 11 , wherein the dummy pattern extends in a same direction that the plurality of word lines extend.

17. The nonvolatile memory device of claim 11 , wherein the dummy pattern extends in a direction that intersects a direction in Which the plurality of word lines extend.

18. The nonvolatile memory device of claim 11 , wherein the dummy pattern extends in a direction in which the plurality of word lines extend and a direction that intersects the direction in which the plurality of word lines extend.

19. A nonvolatile memory system comprising:
a main substrate;
a nonvolatile memory device on the main substrate; and
a controller electrically connected to the nonvolatile memory device on the main substrate,
wherein the nonvolatile memory device includes:
an upper insulating layer;
a first substrate on the upper insulating layer;
an upper interlayer insulating layer on the first substrate;
a plurality of word lines stacked on the first substrate in a first direction and extending through a partial portion of the upper interlayer insulating layer;
a lower interlayer insulating layer on the upper interlayer insulating layer;
a second substrate on the lower interlayer insulating layer;
a lower insulating layer on the second substrate; and
a dummy pattern composed of dummy material, the dummy pattern is disposed in a trench formed in at least one of the first and second substrates, wherein the trench is formed on at least one of a surface where the upper insulating layer meets the first substrate and a surface where the lower insulating layer meets the second substrate, the trench extending solely within the at least one of the first and second substrates.

20. The nonvolatile memory system of claim 19 , wherein:
a thinning process is performed on at least one of the first substrate and the second substrate; and
the trench is formed in the at least one of the first substrate and the second substrate which has been subjected to the thinning process.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Sung-Min
• Kim Ji Won
• Ahn Jae Ho
• Lim Joon-Sung
• Sung Suk Kang

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title