Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same

Patent metadata

Field	Value
Publication number	US-2020335487-A1
Application number	US-202016917526-A
Country	US
Kind code	A1
Filing date	Jun 30, 2020
Priority date	Mar 1, 2019
Publication date	Oct 22, 2020
Grant date	—

Abstract

A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.

First claim

What is claimed is:

1 . A method of forming a semiconductor structure, comprising:
forming a plurality of grooves in a front surface of a carrier substrate; forming a sacrificial cover layer over the plurality of grooves by anisotropically depositing a sacrificial cover material, wherein laterally-extending cavities encapsulated by the sacrificial cover layer and the carrier substrate are formed in the plurality of grooves; attaching a first single crystalline semiconductor layer over the sacrificial cover layer; forming first semiconductor devices on the first single crystalline semiconductor layer; forming first dielectric material layers embedding first metal interconnect structures and first bonding pads on the first semiconductor devices; and detaching the carrier substrate from an assembly comprising the first single crystalline semiconductor layer, the first semiconductor devices, and the first dielectric material layers by flowing an etchant that selectively etches a material of the sacrificial cover layer into the plurality of grooves

2 . The method of claim 1 , further comprising:
forming a silicon oxide layer on the first single crystalline semiconductor layer; and attaching the silicon oxide layer over the sacrificial cover layer, wherein the silicon oxide layer is interposed between the first single crystalline semiconductor layer and the sacrificial cover layer.

3 . The method of claim 2 , further comprising:
forming a silicate glass capping layer on the sacrificial cover layer; and bonding the silicon oxide layer to the silicate glass capping layer by performing an oxide-to-oxide bonding process.

4 . The method of claim 2 , further comprising:
providing a single crystalline semiconductor substrate; forming a hydrogen implanted layer in the single crystalline semiconductor substrate, wherein the single crystalline semiconductor substrate is divided into the first single crystalline semiconductor layer and an additional single crystalline semiconductor layer; and cleaving off the additional single crystalline semiconductor layer from the first single crystalline semiconductor layer after attaching the first single crystalline semiconductor layer over the sacrificial cover layer.

5 . The method of claim 2 , wherein:
the silicon oxide layer is formed on a first horizontal surface of the first single crystalline semiconductor layer; and the first semiconductor devices are formed on a second horizontal surface of the first single crystalline semiconductor layer that is located on an opposite side of the first horizontal surface of the first single crystalline semiconductor layer.

6 . The method of claim 1 , further comprising:
forming second semiconductor devices on a second single crystalline semiconductor layer; forming second dielectric material layers embedding second metal interconnect structures and second bonding pads on the second semiconductor devices; and bonding the second bonding pads to the first bonding pads.

7 . The method of claim 6 , wherein the assembly further comprises the second dielectric material layers, the second semiconductor devices, and the second single crystalline semiconductor layer.

8 . The method of claim 6 , wherein:
a first set of devices selected from the first semiconductor devices and the second semiconductor devices comprise memory devices; and a second set of devices selected from the first semiconductor devices and the second semiconductor devices comprise logic devices configured to control operation of the memory devices, wherein the first metal interconnect structures, the second metal interconnect structures, the first bonding pads, and the second bonding pads provide electrically conductive paths between the memory devices and the logic devices.

9 . The method of claim 8 , wherein the memory devices are formed by:
forming an alternating stack of insulating layers and spacer material layers, wherein the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers; forming memory openings vertically extending through the alternating stack; and forming memory opening fill structures in the memory openings, wherein each of the memory opening fill structures comprises a respective vertical semiconductor channel and a respective memory film.

10 . The method of claim 6 , further comprising;
providing a single crystalline semiconductor substrate; forming a silicon oxide layer on the single crystalline semiconductor substrate; and forming a hydrogen implanted layer in the single crystalline semiconductor substrate by implanting hydrogen atoms through the silicon oxide layer, wherein the single crystalline semiconductor substrate is divided into the second single crystalline semiconductor layer contacting the silicon oxide layer and an additional single crystalline semiconductor layer.

11 . The method of claim 10 , further comprising;
attaching a handle substrate to the second single crystalline semiconductor layer through the silicon oxide layer; and cleaving off the additional single crystalline semiconductor layer from the second single crystalline semiconductor layer after attaching the handle substrate to the second single crystalline semiconductor layer.

12 . The method of claim 11 , wherein the handle substrate comprises an insulating material, a metallic material, a polycrystalline semiconductor material, or a single crystalline semiconductor material having a crystallographic defect density that is at least three times a crystallographic defect density of the single crystalline semiconductor layer.

13 . The method of claim 1 , wherein the sacrificial cover layer is formed by a non-conformal deposition process that deposits the sacrificial cover material at a lesser thickness on sidewalls of the plurality of grooves than on the front surface of the carrier substrate.

14 . The method of claim 13 , wherein the sacrificial cover material comprises borosilicate glass or organosilicate glass.

15 . The method of claim 1 , wherein:
the plurality of grooves comprises a network of a first subset of the grooves laterally extending along a first horizontal direction and a second subset of the grooves laterally extending along a second horizontal direction; and each of the grooves extends to a periphery of the carrier substrate.

16 . A semiconductor structure comprising a memory die bonded to a support die, wherein:
the memory die comprises an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and comprising a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material; and the support die comprises a peripheral circuitry.

17 . The semiconductor structure of claim 16 , wherein:
the single crystalline channel semiconductor material comprises single crystal silicon; and a crystallographic orientation of the single crystalline channel semiconductor material and a crystallographic orientation of the single crystalline semiconductor layer having a same Miller index are parallel to one other for each respective Miller index.

18 . The semiconductor structure of claim 17 , wherein:
the memory die further comprises drain regions comprising a single crystalline drain semiconductor material in epitaxial alignment with the single crystalline channel semiconductor material of an

Assignees

• Sandisk Technologies Llc

Inventors

• RAJASHEKHAR Adarsh
• Makala Raghuveer S
• Zhou Fei

Classifications

• H10D62/83

  being Group IV materials, e.g. B-doped Si or undoped Ge · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title