Semiconductor device

Patent metadata

Field	Value
Publication number	US-9548316-B2
Application number	US-201514959209-A
Country	US
Kind code	B2
Filing date	Dec 4, 2015
Priority date	Dec 9, 2014
Publication date	Jan 17, 2017
Grant date	Jan 17, 2017

Abstract

A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a logic structure including a logic circuit at an upper part of the semiconductor substrate in a circuit region of the device, and lower insulation covering the logic circuit;
a memory structure disposed on the logic structure; and
a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region.

2. The semiconductor device of claim 1 , wherein the memory structure comprises:
a semiconductor layer;
a stack including a plurality of electrodes vertically stacked on the semiconductor layer; and
a plurality of vertical pillars extending through the stack.

3. The semiconductor device of claim 2 , wherein the memory structure further comprises: a respective data storage section interposed between each of the vertical pillars and the electrodes.

4. The semiconductor device of claim 3 , further comprising:
upper insulation covering the stack;
first upper interconnections disposed in the upper insulation and connected to the vertical pillars, respectively; and
first plugs connecting the logic circuit to the first upper interconnections,
wherein the first plugs are disposed in a connection region of the device beside the circuit region.

5. The semiconductor device of claim 4 , further comprising:
second upper interconnections disposed in the upper insulation and connected to the electrodes, respectively; and
second plugs connecting the logic circuit to the second upper interconnections,
wherein the second plugs are disposed in the connection region.

6. The semiconductor device of claim 5 , wherein the lower insulation extends on the semiconductor substrate in the connection region, and
the stress relaxation structure terminates at a boundary between the circuit region and the connection region so as to not extend over the lower insulation in the connection region, and
the semiconductor device further comprises:
intermediate insulation disposed on the lower insulation in the connection region.

7. The semiconductor device of claim 6 , wherein the first and second plugs extend through the intermediate insulation.

8. The semiconductor device of claim 3 , wherein the stack is elongated in a first direction parallel to an upper surface of the semiconductor layer, and
the semiconductor layer has a common source region disposed at a side of the stack.

9. The semiconductor device of claim 8 , further comprising:
a common source line connected to the common source region and extending longitudinally in the first direction.

10. The semiconductor device of claim 3 , wherein each of the vertical pillars comprises:
vertical portions extending through the stack; and
a horizontal portion disposed under the stack and connecting the vertical portions to each other.

11. The semiconductor device of claim 10 , wherein the stack is elongated in a first direction parallel to an upper surface of the semiconductor layer, and
the electrodes comprise:
word lines on the semiconductor layer; and
a string selection line and a ground selection line disposed on the word lines and spaced apart from each other in a second direction parallel to the upper surface of the semiconductor layer and intersecting the first direction.

12. The semiconductor device of claim 1 , wherein the stress relaxation structure comprises material having compressive stress.

13. The semiconductor device of claim 12 , wherein the stress relaxation structure comprises a silicon nitride layer or a silicon oxynitride layer.

14. The semiconductor device of claim 1 , wherein the stress relaxation structure comprises material having tensile stress.

15. The semiconductor device of claim 14 , wherein the material of the stress relaxation structure has a dielectric constant lower than that of silicon oxide.

16. The semiconductor device of claim 14 , wherein the material of the stress relaxation structure is a porous material.

17. The semiconductor device of claim 1 , wherein the stress relaxation structure defines a cavity between the logic structure and the memory structure in the circuit region.

18. The semiconductor device of claim 17 , wherein the stress relaxation structure further comprises a support extending between the logic structure and the memory structure and delimiting the cavity.

19. The semiconductor device of claim 18 , wherein the support comprises at least one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, poly-crystalline silicon, and metals.

20. The semiconductor device of claim 17 , wherein the stress relaxation structure further comprises: a capping layer between the cavity and the memory structure.

Assignees

• Lim Joon-Sung
• Yun Jang-Gn
• Bae Sunghoon
• Yun Jaesun
• Chang Kyu-Baik
• Samsung Electronics Co Ltd

Inventors

• Lim Joon-Sung
• Yun Jang-Gn
• Bae Sunghoon
• Yun Jaesun
• Chang Kyu-Baik

Classifications

• H01L27/0688

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title