Three-dimensional memory devices having a plurality of NAND strings

Patent metadata

Field	Value
Publication number	US-10283452-B2
Application number	US-201815934730-A
Country	US
Kind code	B2
Filing date	Mar 23, 2018
Priority date	Sep 15, 2017
Publication date	May 7, 2019
Grant date	May 7, 2019

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for forming the 3D memory devices are disclosed. In an example, a NAND memory device includes a substrate, a plurality of NAND strings on the substrate, one or more peripheral devices above the NAND strings, a single crystalline silicon layer above the peripheral devices, and one or more interconnect layers between the peripheral devices and the NAND strings. In some embodiments, the NAND memory device includes a bonding interface at which an array interconnect layer contacts a peripheral interconnect layer.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a substrate;
a plurality of NAND strings, wherein a first surface of the plurality of NAND strings opposes a second surface of the plurality of NAND strings, and the second surface of the plurality of NAND strings is in contact with a first surface of the substrate;
one or more first interconnect layers, wherein a first surface of the one or more first interconnect layers opposes a second surface of the one or more first interconnect layers, and the second surface of the one or more first interconnect layers is in contact with the first surface of the plurality of NAND strings;
one or more peripheral devices, wherein a first surface of the one or more peripheral devices opposes a second surface of the one or more peripheral devices, and the second surface of the one or more peripheral devices is in contact with the first surface of the one or more first interconnect layers; and
a single crystalline silicon layer, wherein a first surface of the single crystalline silicon layer opposes a second surface of the single crystalline silicon layer, and the second surface of the single crystalline silicon layer is in contact with the first surface of the one or more peripheral devices.

2. The 3D memory device of claim 1 , wherein the one or more peripheral devices comprise one or more MOSFET devices.

3. The 3D memory device of claim 1 , further comprising an alternating conductor/dielectric stack, wherein each of the plurality of NAND strings comprises:
a semiconductor channel extending vertically through the alternating conductor/dielectric stack;
a tunneling layer between the alternating conductor/dielectric stack and the semiconductor channel; and
a storage layer between the tunneling layer and the alternating conductor/dielectric stack.

4. The 3D memory device of claim 3 , further comprising a first contact, wherein the first contact extends vertically through the alternating conductor/dielectric stack and comprises a lower end in contact with the substrate.

5. The 3D memory device of claim 1 , further comprising a second interconnect layer in contact with the first surface of the single crystalline silicon layer, wherein the second interconnect layer comprises one or more layers of conductor layers formed in one or more dielectric layers.

6. The 3D memory device of claim 1 , wherein a NAND string of the plurality of NAND strings comprises a first NAND string in contact with a second NAND string.

7. The 3D memory device of claim 6 , wherein the NAND string and the another NAND string are electrically connected by a conductor.

8. The 3D memory device of claim 1 , further comprising a through silicon contact, wherein the through silicon contact extends vertically through the single crystalline silicon layer, and wherein the through silicon contact electrically connects with an interconnect layer of the one or more first interconnect layers on one end of the through silicon contact.

9. The 3D memory device of claim 1 , wherein the single crystalline silicon layer comprises a doped region and an isolation region.

10. The 3D memory device of claim 1 , wherein each of the plurality of NAND strings comprises an epitaxial plug at a lower end of the each of the plurality of NAND strings.

11. The 3D memory device of claim 10 , wherein the epitaxial plugs of the plurality of NAND strings contact a doped region in the substrate.

12. The 3D memory device of claim 10 , wherein the second surface of the plurality of NAND strings comprise surfaces of the epitaxial plugs.

13. The 3D memory device of claim 1 , further comprising a plurality of contacts, wherein each contact of the plurality of contacts is in contact with the first surface of the plurality of NAND strings.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Zhu Jifeng
• Lu Zhenyu
• Chen Jun
• Hu Yushi
• Tao Qian
• Yang Simon Shi-Ning
• Yang Steve Wiyi

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/4421

  the principal metal being copper · CPC title

• H10W20/4405

  the principal metal being aluminium · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title