Semiconductor device

Patent metadata

Field	Value
Publication number	US-10529736-B2
Application number	US-201816138416-A
Country	US
Kind code	B2
Filing date	Sep 21, 2018
Priority date	Dec 6, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions. The plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines.

First claim

What is claimed is:

1. A 3-dimensional semiconductor memory device comprising:
a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction;
a stacked memory cell array formed on the semiconductor substrate;
a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction;
an upper insulating layer formed above the plurality of memory cell structures and separation lines; and
a passivation layer formed above the upper insulating layer, wherein:
the passivation layer includes a plurality of first regions having a first vertical thickness,
a plurality of gap regions in the passivation layer are formed between the plurality of first regions, and
the plurality of first regions vertically overlap the plurality of memory cell structures, and the plurality of gap regions vertically overlap the plurality of separation lines.

2. The semiconductor memory device of claim 1 , wherein:
the plurality of gap regions comprise a plurality of second regions of the passivation layer having a second vertical thickness different from the first vertical thickness.

3. The semiconductor memory device of claim 2 , wherein:
the stacked memory cell array is a vertical NAND memory cell array, and the plurality of memory cell structures are a plurality of gate stack structures each including a plurality of gate electrode layers alternately formed with a plurality of interlayer insulating layers on the substrate in a vertical stack.

4. The semiconductor memory device of claim 2 , wherein:
the first regions combined with the second regions are arranged to reduce warpage of the semiconductor memory device in the first direction and to reduce warpage of the semiconductor memory device in the second direction.

5. The semiconductor memory device of claim 4 , wherein:
the first regions combined with the second regions reduce warpage in the first direction by a greater amount than the first regions combined with the second regions reduce warpage in the second direction.

6. The semiconductor memory device of claim 2 , wherein:
the first vertical thickness is larger than the second vertical thickness.

7. The semiconductor memory device of claim 1 , wherein:
the stacked memory cell array is a vertical NAND memory cell array, and the plurality of memory cell structures are a plurality of gate stack structures each including a plurality of gate electrode layers alternately formed with a plurality of interlayer insulating layers on the substrate in a vertical stack; and
the first regions combined with the gap regions are arranged to reduce warpage of the semiconductor memory device in the first direction and to reduce warpage of the semiconductor memory device in the second direction.

8. The semiconductor memory device of claim 1 , wherein:
the passivation layer includes:
a first surface that is continuous and that is flat or curved; and
a second surface opposite the first surface and that has a step shape.

9. The semiconductor memory device of claim 1 , wherein:
the first regions are first line patterns extending in the first direction and having a first width in the second direction, and
the gap regions are second line patterns extending in the first direction that have a smaller vertical thickness than the first regions and that have a second width in the second direction, the second width being smaller than the first width.

10. A vertical NAND (VNAND) semiconductor device comprising:
a semiconductor substrate;
a plurality of gate electrode layers alternately formed with a plurality of interlayer insulating layers on the substrate in a vertical stack, and forming a plurality of gate stack structures extending in a first horizontal direction and separated from each other in a second horizontal direction perpendicular to the first direction;
a plurality of vertical channels passing through each of the plurality of gate stack structures, wherein the plurality of vertical channels form transistor strings;
a plurality of separation areas extending in the first horizontal direction and arranged in the second horizontal direction between the plurality of gate stack structures to separate the gate stack structures from each other;
an upper insulating layer formed above the plurality of gate electrode layers; and
a passivation layer formed above the upper insulating layer,
wherein:
the passivation layer includes a plurality of first regions having a first vertical thickness, and
a plurality of gap regions in the passivation layer are formed between the plurality of first regions, and
wherein the plurality of first regions vertically overlap the plurality of gate stack structures, and the plurality of gap regions vertically overlap the plurality of separation areas.

11. The semiconductor device of claim 10 , wherein:
the plurality of gap regions comprise a plurality of second regions of the passivation layer having a second vertical thickness different from the first vertical thickness.

12. The semiconductor device of claim 11 , wherein:
the first vertical thickness is larger than the second vertical thickness; and
a width in the second horizontal direction of each first region is larger than a width in the second horizontal direction of each of second region.

13. The semiconductor device of claim 12 , wherein:
a ratio of the first vertical thickness to the second vertical thickness is between 5:3 and 5:4.

14. The semiconductor device of claim 10 , wherein:
the passivation layer includes:
a first surface that is continuous and that is flat or curved; and
a second surface opposite the first surface and that has a step shape.

15. The semiconductor device of claim 10 , wherein:
the first regions are first line patterns extending in the first horizontal direction; and
the gap regions are second line patterns extending in the first horizontal direction and wider in the second horizontal direction than the first line patterns.

16. The semiconductor device of claim 10 , wherein:
the passivation layer is patterned to reduce the amount of warpage of the semiconductor device in the first horizontal direction while limiting the warpage of the semiconductor device in the second horizontal direction.

17. A vertical NAND (VNAND) semiconductor device comprising:
a semiconductor substrate;
a plurality of gate stack structures formed on the semiconductor substrate, the plurality of gate stack structures extending lengthwise in a first direction and separated from each other in a second direction perpendicular to the first direction;
a plurality of vertical channels passing through each of the plurality of gate stack structures, wherein the plurality of vertical channels form transistor strings;
a plurality of separation areas extending lengthwise in the first direction and arranged in the second direction between the plurality of gate stack structures to separate the gate stack structures from each other;
an upper insulating layer formed above the plurality of gate stack structures; and
a passivation layer formed above the upper insulating layer,
wherein the passivation layer includes a plurality of first line patterns extending in the first direction and having a first vertical thickness and includes a plurality of second line patterns having a second vertical thickness smaller than t

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Min Sung
• Joo Heung Jin
• Kim Kwan Yong
• Park Jin Woo
• Song Du Heon
• Lee He Jueng
• Jung Myung Ho

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/1157

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic