Semiconductor device fabrication method

Patent metadata

Field	Value
Publication number	US-11710780-B2
Application number	US-202117164253-A
Country	US
Kind code	B2
Filing date	Feb 1, 2021
Priority date	Jun 1, 2016
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

Semiconductor device fabrication method is provided. The method includes providing a substrate; forming a first semiconductor layer on the substrate; forming a stack of semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second and third semiconductor layers having at least a common compound element, and the third semiconductor layer and the first semiconductor layer having a same semiconductor compound; performing an etching process to form a fin structure; performing a selective etching process on the second semiconductor layer to form a first air gap between the first semiconductor layer and the third semiconductor layer and a second air gap between each of adjacent third semiconductor layers in the stack of one or more semiconductor layer structures; and filling the first and second air gaps with an insulator layer.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first semiconductor layer on the substrate;
forming a stack of one or more semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second and third semiconductor layers having at least a common compound element, and the third semiconductor layer and the first semiconductor layer having a same semiconductor compound;
performing an etching process on the stack of one or more semiconductor layer structures and the first semiconductor layer to form a fin structure;
performing a selective etching process on the second semiconductor layer to form a first air gap between the first semiconductor layer and the third semiconductor layer and a second air gap between each of adjacent third semiconductor layers in the stack of one or more semiconductor layer structures; and
filling the first and second air gaps with an insulator layer.

2. The method of claim 1 , further comprising, prior to performing the etching process on the stack of one or more semiconductor layer structures and the first semiconductor layer to form the fin structure:
etching the second semiconductor layer in each of the one or more semiconductor layer structures; and
performing the selective etching process comprises removing a portion of the second semiconductor layer in each of the one or more semiconductor layer structures.

3. The method of claim 1 , further comprising forming a fourth semiconductor layer on the substrate, wherein the first semiconductor layer is formed on the fourth semiconductor layer.

4. The method of claim 3 , wherein the fourth semiconductor layer comprises InAlAs.

5. The method of claim 1 , wherein:
the substrate comprises silicon;
the first semiconductor layer comprises germanium tin;
the second semiconductor layer comprises germanium;
the third semiconductor layer comprises germanium tin;
the insulator layer comprises silicon oxide.

6. The method of claim 1 , wherein the second and third semiconductor layers each comprise a group III-V compound.

7. The method of claim 1 , wherein the second semiconductor layer comprises three compound elements, and the third semiconductor layer comprises two compound elements.

8. The method of claim 1 , wherein the third semiconductor layer comprises InP.

9. The method of claim 1 , further comprising forming a high-k dielectric layer on the substrate, wherein the first semiconductor layer is formed on the high-k dielectric layer.

10. The method of claim 9 , wherein the high-k dielectric material comprises HfO2.

11. The method of claim 1 , wherein:
the first semiconductor layer comprises InGaAs;
the second semiconductor layer comprises InGaAs; and
the first insulator layer comprises a high-k dielectric material.

12. The method of claim 1 , wherein performing the etching process comprises:
removing a portion of the fin structure to form a trench on opposite sides of the fin structure;
filling the trench with a second insulator layer.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Zhang Haiyang
• Wang Yan

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10D86/215

  comprising FinFETs · CPC title

• H10D86/011

  comprising FinFETs · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/834

  comprising FinFETs · CPC title