Methods of forming semiconductor devices and FinFET devices, and FinFET devices

Patent metadata

Field	Value
Publication number	US-9355920-B2
Application number	US-201414203213-A
Country	US
Kind code	B2
Filing date	Mar 10, 2014
Priority date	Mar 10, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Methods of forming semiconductor devices and fin field effect transistors (FinFETs), and FinFET devices, are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a barrier material comprising AlInAsSb over a substrate, and forming a channel material of a transistor over the barrier layer.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a template material over a substrate;
forming a barrier material comprising AlInAsSb over the template material after deoxidizing the template material; and
forming a channel material of a transistor over the barrier material,
wherein a lower surface of the template material contacts the substrate, and an upper surface of the template material opposing the lower surface contacts the barrier material, wherein the template material extends continuously without an interface from the substrate to the barrier material.

2. The method according to claim 1 , wherein forming the barrier material comprises forming a barrier material comprising about 0.5% to about 15% of In.

3. The method according to claim 1 , wherein forming the barrier material comprises forming a barrier material comprising a thickness of about 4 nm to about 80 nm.

4. The method according to claim 1 , wherein forming the channel material comprises forming a channel material comprising a thickness of about 3 nm to about 40 nm.

5. The method according to claim 1 , wherein forming the template material comprises forming a template material comprising a thickness of about 10 nm to about 100 nm.

6. The method according to claim 1 , wherein forming the channel material comprises epitaxially growing the channel material, and wherein the barrier material comprises a seed layer for the epitaxial growth of the channel material.

7. The method according to claim 1 , wherein forming the channel material comprises forming a channel of a planar transistor or a fin field effect transistor (FinFET).

8. The method according to claim 1 , wherein forming the template material comprises forming the template material using a group III-V material.

9. The method according to claim 1 , wherein a lattice of the barrier material is substantially matched to a lattice of the template material.

10. A method of forming a fin field effect transistor (FinFET) device, the method comprising:
forming shallow trench isolation (STI) regions in a substrate;
recessing a portion of the substrate between two of the STI regions;
forming a template material over the substrate;
forming a barrier material comprising AlInAsSb over the template material after deoxidizing the template material, wherein the deoxidizing comprises heating the template material in the presence of an As or P flux;
forming a channel material over the barrier material;
recessing the STI regions, wherein a portion of the channel material disposed over top surfaces of remaining portions of the STI regions forms a semiconductor fin;
forming a gate dielectric on sidewalls and a top surface of the semiconductor fin; and
forming a gate electrode over the gate dielectric.

11. The method according to claim 10 , wherein deoxidizing the template material comprises heating the FinFET device at a temperature of about 500 degrees C. to about 600 degrees C.

12. The method according to claim 10 , further comprising monitoring the surface of the template material while deoxidizing the template material to ensure a stable surface reconstruction of the template material.

13. The method according to claim 12 , wherein monitoring the surface of the template material comprises using reflection high-energy electron diffraction (RHEED).

14. The method according to claim 10 , wherein forming the barrier material comprises introducing fluxes of As e , Sb, In, and Al at a temperature of about 450 degrees C. to about 560 degrees C.

15. A method of forming a semiconductor device, the method comprising:
forming a template material over a substrate, the template material absorbing lattice mismatches with the substrate;
epitaxially forming a barrier material over the template material, the barrier material having a lattice that is matched to the template material;
epitaxially forming a channel material over the barrier material using the barrier material as a seed layer, the channel material comprising a high mobility conductive or semiconductive material;
forming a gate dielectric over the channel material; and
forming a gate electrode over the gate dielectric.

16. The method according to claim 15 , wherein the barrier material comprises In and is free of point defects.

17. The method according to claim 15 , wherein the barrier material comprises AlInAsSb.

18. The method according to claim 15 , wherein the channel material comprises a material selected from the group consisting of InAs, InGaAs, GaSb, InGaSb, InSb, and combinations thereof.

19. The method accordingly to claim 15 , further comprising:
deoxidizing the template material before the epitaxially forming the barrier material.

20. The method according to claim 19 , wherein the deoxidizing the template material is performed in the presence of an As or P flux.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Holland Martin Christopher
• Passlack Matthias
• Oxland Richard Kenneth

Classifications

• H10P95/904

  of Group III-V semiconductors · CPC title

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10D62/852

  being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP · CPC title

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title

• H10D62/82

  Heterojunctions · CPC title