Nanowire FET with tensile channel stressor

Patent metadata

Field	Value
Publication number	US-9601576-B2
Application number	US-201414256225-A
Country	US
Kind code	B2
Filing date	Apr 18, 2014
Priority date	Apr 18, 2014
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

Fin stacks including a silicon germanium alloy portion and a silicon portion are formed on a surface of a substrate. Sacrificial gate structures are then formed straddling each fin stack. Silicon germanium alloy portions that are exposed are oxidized, while silicon germanium alloy portions that are covered by the sacrificial gate structures are not oxidized. A dielectric material having a topmost surface that is coplanar with a topmost surface of each sacrificial gate structure is formed, and thereafter each sacrificial gate structure is removed. Non-oxidized silicon germanium alloy portions are removed suspending silicon portions that were present on each non-oxidized silicon germanium alloy portion. A functional gate structure is then formed around each suspended silicon portion. The oxidized silicon germanium alloy portions remain and provide stress to a channel portion of the suspended silicon portions.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a silicon structure suspended above a topmost surface of an insulator layer;
a functional gate structure positioned around said silicon structure suspended above said topmost surface of said insulator layer;
a source side non-suspended silicon structure located on one side of said functional gate structure and positioned on a surface of an oxidized silicon germanium alloy material, wherein outermost vertical sidewalls of said source side non-suspended silicon structure are vertically coincident to outermost vertical sidewalls of said oxidized silicon germanium alloy material; and
a drain side non-suspended silicon structure located on another side of said functional gate structure and positioned on a surface of another oxidized silicon germanium alloy material, wherein outermost vertical sidewalls of said drain-side non-suspended silicon structure are vertically coincident to outermost vertical sidewalls of said another oxidized silicon germanium alloy material, and wherein said oxidized silicon germanium alloy material and said another oxidized silicon germanium alloy material introduce a strain into a channel portion of said silicon structure suspended above said topmost surface of said insulator layer.

2. The semiconductor structure of claim 1 , wherein a bottommost surface of said oxidized silicon germanium alloy material and a bottommost surface of said another oxidized silicon germanium alloy material are in direct physical contact with portions of said topmost surface of said insulator layer.

3. The semiconductor structure of claim 1 , further comprising a raised source region located on a topmost surface of said source side non-suspended silicon structure, and a raised drain region located on a topmost surface of said drain side non-suspended silicon structure.

4. The semiconductor structure of claim 1 , further comprising a dielectric spacer located on vertical sidewalls of said functional gate structure.

5. The semiconductor structure of claim 1 , wherein said functional gate structure comprises a gate dielectric material and a gate conductor.

6. The semiconductor structure of claim 5 , wherein said gate dielectric material is located on a top surface, a bottom surface and sidewall surfaces of said silicon structure suspended above said topmost surface of said insulator layer.

7. The semiconductor structure of claim 2 , further comprising a dielectric material surrounding said functional gate structure, wherein a topmost surface of said dielectric material is coplanar with a topmost surface of said functional gate structure.

8. The semiconductor structure of claim 1 , wherein said insulator layer is positioned on a topmost surface of a handle substrate.

9. The semiconductor structure of claim 1 , wherein said oxidized silicon germanium alloy material and said another oxidized silicon germanium alloy material each consists of elements of Si, Ge and O.

10. The semiconductor structure of claim 1 , wherein said oxidized silicon germanium alloy material and said another oxidized silicon germanium alloy portion introduce stress into said silicon structure.

11. The semiconductor structure of claim 1 , wherein said oxidized silicon germanium alloy material and said another oxidized silicon germanium alloy material comprise from 10 atomic percent germanium to 90 atomic percent germanium.

Assignees

• IBM

Inventors

• Lauer Isaac
• Lin Chung-Hsun
• Sleight Jeffrey W

Classifications

• H01L29/66795

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic

• H01L29/0669

  Electricity · mapped topic

• H01L29/1054 Primary

  Electricity · mapped topic