Segregated FinFET structure and manufacturing method

Patent metadata

Field	Value
Publication number	US-9425278-B2
Application number	US-201414502912-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Jun 17, 2014
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

A semiconductor device includes a semiconductor fin on a substrate. The semiconductor fin includes a stack of alternating layers of first and second materials that induce stress or strain to the channel of the semiconductor device for implementing a strained FinFET. The first and second materials are different. The second material layers include lateral recesses filled with an insulating layer to form an isolated FinFET structure to further induce stress in the channel region to improve the performance of the semiconductor device.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device comprising:
providing a substrate;
forming a semiconductor fin having a laminated structure on the substrate, the laminated structure having a stack of alternating first material layers and second material layers;
forming a shallow trench insulation structure on opposite sides of the semiconductor fin;
selectively removing portions of the second material layers to obtain lateral recesses with respect to the first material layers; and
forming an insulating layer filling the lateral recesses and directly on an upper surface and side surfaces of the semiconductor fin protruding over a surface of the shallow trench insulation structure as a gate insulation layer, wherein the insulating layer filling the lateral recesses has a thickness greater than a thickness of the gate insulating layer.

2. The method of claim 1 , wherein the first material layers comprise SiGe layers and the second material layers comprise Si layers.

3. The method of claim 2 , wherein the first material layers comprises a concentration of Ge in a range between 20 and 50 percent.

4. The method of claim 1 , wherein the first material layers comprise SiGe layers and the second material layers comprise Ge layers.

5. The method of claim 1 , wherein the substrate is a silicon substrate or a silicon-on-insulator (SOI) substrate.

6. The method of claim 1 , wherein forming the semiconductor fin comprises:
alternatively depositing at least one first material layer and at least one second material layer; and
patterning and etching the laminated structure to form the semiconductor fin.

7. The method of claim 1 , wherein the semiconductor device is a FinFET having a tensile stress or a compressive stress.

8. The method of claim 1 , wherein selectively removing comprises a wet etching.

9. The method of claim 8 , wherein the wet etching is performed at a temperature at about 70 degrees C. using an alkaline etchant.

10. The method of claim 9 , wherein the alkaline etchant comprises at least one of KOH, propanol, and K 2 Cr 2 O 7 , or at least one of NH 4 NO 3 and NH 4 OH.

11. A semiconductor device comprising:
a substrate;
a semiconductor fin on the substrate, the semiconductor fin having a stack of alternating first material layers and second material layers, the second material layers comprising lateral recesses with respect to the first material layers;
a shallow trench insulating structure disposed on opposite sides of the semiconductor fin; and
an insulating layer filling the lateral recesses and directly on an upper surface and side surfaces of the semiconductor fin protruding over a surface of the shallow trench insulation structure as a gate insulation layer, wherein the insulating layer filling the lateral recesses has a thickness greater than a thickness of the gate insulating layer.

12. The semiconductor device of claim 11 , wherein the first material layers comprise SiGe layers and the second material layers comprise Si layers.

13. The semiconductor device of claim 12 , wherein the first material layers comprise a concentration of Ge in a range between 20 and 50 percent.

14. The semiconductor device of claim 11 , wherein the first material layers comprise SiGe layers and the second material layers comprise Ge layers.

15. The semiconductor device of claim 11 , wherein the semiconductor device is a FinFET having a tensile stress or a compressive stress.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Mieno Fumitake

Classifications

• H10D64/01322

  the conductor contacting the insulator having a lateral variation in doping, composition or deposition steps · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title