Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9755055-B2
Application number	US-201414568227-A
Country	US
Kind code	B2
Filing date	Dec 12, 2014
Priority date	Jun 11, 2010
Publication date	Sep 5, 2017
Grant date	Sep 5, 2017

Abstract

A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first insulating layer;
a gate electrode layer provided on the first insulating layer;
a second insulating layer provided on the gate electrode layer;
a columnar inner insulating layer extending in a stacking direction of the first insulating layer, the gate electrode layer and the second insulating layer;
a third insulating layer provided between the gate electrode layer and the columnar inner insulating layer; and
a polycrystalline semiconductor layer provided between the third insulating layer and the columnar inner insulating layer,
wherein a crystal lattice spacing of the polycrystalline semiconductor layer in the stacking direction is larger than a crystal lattice spacing in a non-distorted state.

2. The device according to claim 1 , further comprising:
a charge-storage insulating layer provided between the gate electrode layer and the third insulating layer; and
a fourth insulating layer provided between the gate electrode layer and the charge-storage insulating layer.

3. The device according to claim 1 , wherein the polycrystalline semiconductor layer includes silicon.

4. The device according to claim 1 , further comprising:
a source region electrically connected to one end of the polycrystalline semiconductor layer; and
a drain region electrically connected to other end of the polycrystalline semiconductor layer.

5. The device according to claim 1 , wherein the third insulating layer includes at least one of the group consisting of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer and a hafnium oxide layer.

6. The device according to claim 2 , wherein the charge-storage insulating layer includes at least one of the group consisting of a silicon nitride layer and a hafnium oxide layer.

7. The device according to claim 2 , wherein the fourth insulating layer includes at least one of the group consisting of a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer and a hafnium oxide layer.

8. The device according to claim 1 , wherein a tensile strain is induced in the polycrystalline semiconductor layer in the stacking direction.

9. The device according to claim 2 , wherein the polycrystalline semiconductor layer includes silicon.

10. The device according to claim 2 , wherein a tensile strain is induced in the polycrystalline semiconductor layer in the stacking direction.

11. The device according to claim 2 , wherein the polycrystalline semiconductor layer is distorted such that the crystal lattice spacing of the polycrystalline semiconductor layer in the stacking direction is larger than the crystal lattice spacing in the non-distorted state.

Assignees

• Toshiba Kk

Inventors

• Saitoh Masumi
• Numata Toshinori
• Nakabayashi Yukio

Classifications

• H01L27/1203

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L27/11578

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic

• H01L29/7847

  Electricity · mapped topic