Semiconductor memory device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11688779-B2
Application number	US-202117387427-A
Country	US
Kind code	B2
Filing date	Jul 28, 2021
Priority date	Aug 7, 2020
Publication date	Jun 27, 2023
Grant date	Jun 27, 2023

Abstract

A semiconductor memory device includes a substrate having a first active pattern including first and second source/drain regions, a gate electrode intersecting the first active pattern and disposed between the first and second source/drain regions, a bit line intersecting the first active pattern and electrically connected to the first source/drain region, a spacer disposed on a sidewall of the bit line, a contact electrically connected to the second source/drain region and spaced apart from the bit line with the spacer interposed therebetween, an interface layer disposed between the second source/drain region and the contact, and forming an ohmic contact between the second source/drain region and the contact, and a data storage element disposed on the contact. A bottom of the contact is lower than a top surface of the substrate. The contact is formed of a metal, a conductive metal nitride, and/or a combination thereof.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a substrate having a first active pattern including a first source/drain region and a second source/drain region;
a gate electrode intersecting the first active pattern and extending in a first direction;
a bit line intersecting the first active pattern and extending in a second direction crossing the first direction, the bit line electrically connected to the first source/drain region;
a spacer disposed on a sidewall of the bit line;
a contact electrically connected to the second source/drain region, the contact spaced apart from the bit line with the spacer interposed therebetween with a portion of the contact vertically overlapping the bit line;
an interface layer disposed between the second source/drain region and the contact, the interface layer forming an ohmic contact between the second source/drain region and the contact; and
a data storage element disposed on the contact,
wherein a bottom of the contact, which is in contact with the interface layer, is lower than a top surface of the substrate, and
wherein the contact is formed of at least one of a metal, a conductive metal nitride, or a combination thereof.

2. The semiconductor memory device of claim 1 , wherein the contact comprises:
a first metal pattern; and
a second metal pattern disposed between the first metal pattern and the interface layer,
wherein the first metal pattern includes a metal, and
wherein the second metal pattern includes a conductive metal nitride.

3. The semiconductor memory device of claim 2 , wherein a bottom of the first metal pattern is lower than the top surface of the substrate.

4. The semiconductor memory device of claim 1 , wherein the interface layer includes graphene, and
wherein a thickness of the interface layer ranges from about 1 nm to about 5 nm.

5. The semiconductor memory device of claim 1 , wherein the contact includes:
a lower portion located at a level lower than the top surface of the substrate;
an upper portion provided on the lower portion and vertically extending along the spacer; and
a pad portion which is provided on the upper portion and on which the data storage element is placed.

6. The semiconductor memory device of claim 1 , further comprising:
a device isolation layer filling a first trench defining the first active pattern,
wherein the first active pattern and the device isolation layer are recessed to define a contact hole, and
wherein a lower portion of the contact and the interface layer are provided in the contact hole.

7. The semiconductor memory device of claim 6 , wherein the substrate further has a second active pattern,
wherein each of the first and second active patterns has a long axis in a third direction crossing the first and second directions,
wherein the first and second active patterns are adjacent to each other in the third direction,
wherein the device isolation layer fills a second trench between the first and second active patterns, and
wherein the second trench is deeper than the first trench.

8. The semiconductor memory device of claim 1 , further comprising:
a conductive pattern provided under the bit line,
wherein the conductive pattern is connected to the first source/drain region of the first active pattern, and
wherein a bottom surface of the conductive pattern, which is in contact with the first source/drain region, is lower than the bottom of the contact.

9. The semiconductor memory device of claim 1 , wherein the data storage element comprises:
a first electrode provided on a pad portion of the contact;
a second electrode disposed on the first electrode; and
a dielectric layer disposed between the first electrode and the second electrode.

10. The semiconductor memory device of claim 1 , further comprising:
a mask pattern disposed on the bit line,
wherein the interface layer vertically extends from the second source/drain region along the spacer to cover at least a portion of a top surface of the mask pattern.

11. A semiconductor memory device comprising:
a substrate having an active pattern including a first source/drain region and a second source/drain region;
a gate electrode intersecting the active pattern and extending in a first direction;
a line structure intersecting the active pattern and extending in a second direction crossing the first direction, the line structure comprising a bit line electrically connected to the first source/drain region;
a spacer disposed on a sidewall of the line structure;
a metal contact electrically connected to the second source/drain region, the metal contact spaced apart from the bit line with the spacer interposed therebetween;
an interface layer disposed between the second source/drain region and the metal contact; and
a data storage element disposed on the metal contact,
wherein the interface layer includes graphene.

12. The semiconductor memory device of claim 11 , wherein the second source/drain region has a top surface recessed to be lower than a top surface of the substrate, and
wherein the interface layer covers the recessed top surface of the second source/drain region.

13. The semiconductor memory device of claim 11 , further comprising:
a semiconductor pattern disposed between the second source/drain region and the interface layer,
wherein the second source/drain region has a top surface recessed to be lower than a top surface of the substrate, and
wherein the semiconductor pattern is in contact with the recessed top surface of the second source/drain region.

14. The semiconductor memory device of claim 11 , wherein the line structure further comprises a mask pattern on the bit line, and
wherein the interface layer vertically extends from the second source/drain region along the spacer to cover at least a portion of a top surface of the mask pattern.

15. The semiconductor memory device of claim 11 , wherein the metal contact includes:
a lower portion located at a level lower than a top surface of the substrate;
an upper portion provided on the lower portion and vertically extending along the spacer; and
a pad portion which is provided on the upper portion and on which the data storage element is placed.

16. A semiconductor memory device comprising:
a substrate having an active pattern, the active pattern, which has a long axis in a first direction, including a first source/drain region and a pair of second source/drain regions spaced apart from each other in the first direction with the first source/drain region interposed therebetween;
a device isolation layer filling a first trench which is provided in the substrate to define the active pattern;
a pair of gate electrodes intersecting the active pattern and extending in a second direction crossing the first direction, each of the pair of gate electrodes provided in a second trench between the first and second source/drain regions and having a top surface lower than a top surface of the active pattern;
a gate dielectric layer disposed between the active pattern and each of the pair of gate electrodes;
a gate capping layer provided on each of the pair of gate electrodes to fill the second trench;
an insulating layer disposed on the substrate;
a line structure intersecting the active pattern on the insulating layer and extending in a third direction crossing the first and second directions, the line structure comprising:
a conductive pattern penetrating the insulating layer so as to be connected to the first source/drain region;
a bit line disposed on the conductive pattern; and
a barrier patter

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hui-Jung
• Ahn Junhyeok
• Yoon Jae Hyun
• Lee Myeong-Dong
• Lee Seok Hwan
• Han Sunghee
• Heo Inkyoung

Classifications

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title

• H10D62/882

  Graphene · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D64/258 Primary

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title