Method and apparatus for back end of line semiconductor device processing

Patent metadata

Field	Value
Publication number	US-9613854-B2
Application number	US-201514853104-A
Country	US
Kind code	B2
Filing date	Sep 14, 2015
Priority date	Jun 18, 2013
Publication date	Apr 4, 2017
Grant date	Apr 4, 2017

Abstract

A method of forming a device may include: forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line. The method may further include the step of catalytically growing a graphene layer on an exposed surface of the metal line, and depositing an amorphous carbon layer on sidewalls of the opening. The steps of catalytically growing the graphene layer and depositing the amorphous carbon layer may be performed simultaneously.

First claim

What is claimed is:

1. A method of manufacturing a device, the method comprising:
forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line;
catalytically growing a graphene layer on an exposed surface of the metal line; and
depositing an amorphous carbon layer on sidewalls of the opening, wherein the steps of catalytically growing the graphene layer and depositing the amorphous carbon layer are performed simultaneously.

2. The method of claim 1 , wherein a portion of the amorphous carbon layer is disposed laterally adjacent to the graphene layer and the etching stop layer, the portion of the amorphous carbon layer being in physical contact with the metal line.

3. The method of claim 1 , wherein a thickness of the graphene layer is in a range from about 1 Angstrom to about 50 Angstroms.

4. The method of claim 1 , wherein catalytically growing the graphene layer comprises:
depositing an amorphous carbon material over the exposed surface of the metal line, the metal line acting as a catalyst for selective-growth of the graphene layer on the exposed surface of the metal line.

5. The method of claim 1 , wherein catalytically growing the graphene layer comprises a selective chemical vapor deposition (CVD) growth process.

6. The method of claim 1 , further comprising:
filling the opening with a conductive material to form a metal contact.

7. The method of claim 6 , further comprising:
forming a first capping layer over the metal contact, the first capping layer comprising graphene; and
forming a second capping layer over the dielectric layer and laterally adjacent to the first capping layer, the second capping layer comprising amorphous carbon.

8. The method of claim 7 , wherein the first capping layer and the second capping layer are formed at a same time.

9. A method of manufacturing a device, the method comprising:
depositing a metal oxide material over a metal layer to form an etching stop layer;
depositing a first dielectric material over the etching stop layer;
etching a first opening through the etching stop layer and the first dielectric material to expose a surface of a conductive feature formed in the metal layer;
lining sidewalls of the first opening with an amorphous carbon material; and
simultaneous to the lining, forming a graphene layer at a bottom the first opening, the graphene layer contacting the conductive feature.

10. The method of claim 9 , wherein the metal oxide material comprises at least one of hafnium or aluminum.

11. The method of claim 9 , wherein forming the graphene layer comprises at least one of a chemical reduction of graphite oxide, an annealing of single-crystal SiC, or a chemical vapor deposition (CVD) process.

12. The method of claim 9 , wherein a portion of the amorphous carbon material proximal the conductive feature contacts the conductive feature and is laterally adjacent to the etching stop layer and the graphene layer.

13. The method of claim 9 , further comprising:
forming a metal contact in the first opening and over the graphene layer;
forming a capping layer over the metal contact and the first dielectric material, the capping layer having a first portion disposed over and contacting the metal contact;
forming a second dielectric material over the capping layer;
forming a second opening in the second dielectric material, the second opening exposing the first portion of the capping layer; and
filling the second opening with a conductive material to form a via.

14. The method of claim 13 , wherein the capping layer comprises a second portion disposed over and contacting the amorphous carbon material and the first dielectric material.

15. The method of claim 14 , wherein no portion of the second portion of the capping layer is exposed by the second opening.

16. A method of manufacturing a device, the method comprising:
forming an opening through a first dielectric layer to expose a surface of a conductive line in a metal layer;
forming a first amorphous carbon layer over sidewalls of the opening and in peripheral portions of a bottom of the opening; and
forming a first graphene layer in a central portion of the bottom of the opening, the first graphene layer physically contacting the surface of the conductive line and portions of the first amorphous carbon layer disposed in peripheral portions of the bottom of the opening.

17. The method of claim 16 , wherein the steps of forming the first amorphous carbon layer and forming the first graphene layer are performed simultaneously.

18. The method of claim 16 , wherein the first dielectric layer comprises a material selected from a group consisting essentially of oxide, SiO 2 , borophosphosilicate glass (BPSG), TEOS, spin-on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), high-density plasma (HDP) oxide, or plasma-enhanced TEOS (PETEOS).

19. The method of claim 16 , further comprising:
forming a conductive via in the opening, the first amorphous carbon layer and the first graphene layer lining the conductive via;
forming a second amorphous carbon layer over surfaces of the first amorphous carbon layer and the first dielectric layer facing away from the metal layer; and
forming a second graphene layer over a surface of the conductive via facing away from the metal layer.

20. The method of claim 16 , wherein forming the first graphene layer comprises at least one of a chemical reduction of graphite oxide, an annealing of single-crystal SiC, or a chemical vapor deposition (CVD) process.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Shin-Yi
• Lee Hsiang-Huan
• Lee Ming-Han
• Yeh Ching-Fu
• Liou Pei-Yin

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/4462

  Carbon or carbon-containing materials, e.g. graphene · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title

• H10W20/48

  Insulating materials thereof · CPC title