Semiconductor device and method for manufacturing the same

US10483115B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10483115-B2
Application numberUS-201715692528-A
CountryUS
Kind codeB2
Filing dateAug 31, 2017
Priority dateApr 24, 2017
Publication dateNov 19, 2019
Grant dateNov 19, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device, comprising: a non-insulator structure formed in one of a source/drain region and a gate structure; at least one carbon nano-tube (CNT) over the non-insulator structure; a dielectric layer surrounding the CNT; and a graphene-based conductive layer over the at least one CNT. 2. The semiconductor device of claim 1 , further comprising: a conductive material filling interspaces between a plurality of the at least one CNTs. 3. The semiconductor device of claim 2 , wherein the non-insulator structure comprises a metal silicide, and the metal silicide and the conductive material comprise the same metal. 4. The semiconductor device of claim 1 , further comprising: a catalyst layer between the at least one CNT and the non-insulator structure. 5. The semiconductor device of claim 4 , wherein the catalyst layer and the non-insulator structure comprise the same metal. 6. The semiconductor device of claim 1 , further comprising: a catalyst layer between the graphene-based conductive layer and the at least one CNT. 7. The semiconductor device of claim 6 , wherein the catalyst layer wraps around the graphene-based conductive layer. 8. The semiconductor device of claim 1 , further comprising: a conductor, wherein the graphene-based conductive layer wraps around the conductor. 9. The semiconductor device of claim 8 , wherein a top surface of the conductor is substantially level with an end surface of the graphene-based conductive layer. 10. A semiconductor device, comprising: a non-insulator structure; a carbon nano-tube (CNT) electrically connected to the non-insulator structure; a first dielectric layer, the CNT being within the first dielectric layer; a second dielectric layer over the first dielectric layer; and a U-shaped graphene-based conductive layer within the second dielectric layer and electrically connected to the CNT. 11. The semiconductor device of claim 10 , further comprising: a first catalyst layer; and a second catalyst layer, wherein the CNT is in between the first catalyst layer and the second catalyst layer. 12. The semiconductor device of claim 11 , wherein the CNT is in contact with the first catalyst layer. 13. The semiconductor device of claim 11 , wherein the U-shaped graphene-based conductive layer is in contact with the second catalyst layer. 14. The semiconductor device of claim 11 , further comprising: a metal wrapping around the CNT. 15. The semiconductor device of claim 11 , further comprising: a metal, wherein the U-shaped graphene-based conductive layer is disposed on sidewalls and a bottom surface of the metal. 16. A method for manufacturing a semiconductor device, comprising: forming a hole in a first dielectric layer over a non-insulator structure; forming a carbon nano-tube (CNT) in the hole and electrically connected to the non-insulator structure; forming a second dielectric layer over the CNT and the first dielectric layer; forming a trench in the second dielectric layer and exposing a top surface of the CNT; and after forming the trench, forming a graphene-based conductive layer in the trench and electrically connected to the CNT. 17. The method of claim 16 , wherein the forming the CNT comprises: forming a catalyst layer in the hole; and growing the CNT over the catalyst layer. 18. The method of claim 16 , further comprising: filling the hole with a metal after the forming the CNT. 19. The method of claim 16 , wherein the forming the graphene-based conductive layer comprises: forming a catalyst layer in the trench; and growing the graphene-based conductive layer over the catalyst layer. 20. The method of claim 16 , further comprising: filling the trench with a metal after the forming the graphene-based conductive layer.

Assignees

Inventors

Classifications

  • Nanotechnology for materials or surface science, e.g. nanocomposites · CPC title

  • composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon · CPC title

  • Nanotubes · CPC title

  • Carbon, e.g. diamond-like carbon · CPC title

  • Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

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Frequently asked questions

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What does patent US10483115B2 cover?
A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/43. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 19 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).