Semiconductor device with interconnecting structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10510657-B2
Application number	US-201715715327-A
Country	US
Kind code	B2
Filing date	Sep 26, 2017
Priority date	Sep 26, 2017
Publication date	Dec 17, 2019
Grant date	Dec 17, 2019

Abstract

A semiconductor device includes a substrate, a dielectric layer, a via, a line, and a capping layer. The substrate includes at least one conductive layer, in which a top surface of the at least one conductive layer has a first portion and a second portion. The dielectric layer is disposed on the substrate and the first portion of the top surface of the at least one conductive layer. The via is disposed in the dielectric layer on the second portion of the top surface of the at least one conductive layer. The line is disposed on the via and a portion of the dielectric layer. The capping layer is disposed on a top surface of the line and peripherally encloses a side surface of the line, in which the capping layer has an etch selectivity with respect to the line.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate comprising at least one conductive layer, wherein a top surface of the at least one conductive layer has a first portion and a second portion;
forming a first dielectric layer on the substrate and said first portion of the top surface of the at least one conductive layer;
forming a via in the first dielectric layer on said second portion of the top surface of the at least one conductive layer;
forming a first capping layer on a top surface of the via;
forming a line on the first capping layer and a portion of the first dielectric layer; and
forming a second capping layer on a top surface of the line to peripherally enclose a side surface of the line, wherein each of the first capping layer and the second capping layer has an etch selectivity with respect to the line and the second capping layer peripherally encloses the first capping layer.

2. The method of claim 1 , wherein
forming the first dielectric layer comprises forming the first dielectric layer having a via hole which exposes said second portion of the top surface of the at least one conductive layer; and
before forming the via, the method further comprises forming a barrier layer to cover a sidewall and a bottom of the via hole and a top surface of the first dielectric layer.

3. The method of claim 2 , wherein forming the via comprises:
forming a via material layer on the barrier layer to fill the via hole with the via material layer; and
removing a portion of the via material layer which is disposed on the barrier layer on the top surface of the first dielectric layer.

4. The method of claim 1 , wherein each of the first capping layer and the second capping layer is formed from grapheme.

5. The method of claim 4 , wherein each of forming the first capping layer and forming the second capping layer is performed by using an atomic layer deposition process, a chemical vapor deposition process, a plasma-enhanced atomic layer deposition process, or a plasma-enhanced chemical vapor deposition process.

6. The method of claim 1 , wherein after forming the second capping layer, the method further comprises:
forming a second dielectric layer on the first dielectric layer to peripherally enclose the line; and
forming a third dielectric layer on the second dielectric layer and the second capping layer, wherein forming the third dielectric layer comprises forming the third dielectric layer having another via hole over the line.

7. The method of claim 1 , wherein after forming the second capping layer, the method further comprises:
forming a second dielectric layer on the first dielectric layer and the second capping layer to peripherally enclose the line, wherein forming the second dielectric layer comprises forming the second dielectric layer having another via hole over the line.

8. A method, comprising:
forming a conductive layer through a first dielectric layer;
forming a second dielectric layer over the first dielectric layer;
forming a via in the second dielectric layer and over the conductive layer;
forming a metal line over the via;
forming a first graphene layer that wraps around the metal line and that is in contact with a top surface of the second dielectric layer; and
forming a third dielectric layer around the first graphene layer such that a top surface of the third dielectric layer is substantially level with a top surface of the first graphene layer.

9. The method of claim 8 , wherein forming the metal line comprises depositing a metal layer over the conductive layer and etching the metal layer, and wherein forming the first graphene layer is performed after etching the metal layer.

10. The method of claim 8 , wherein forming the first graphene layer is performed such that a portion of the second dielectric layer is free from coverage by the first graphene layer.

11. The method of claim 8 , further comprising:
forming a fourth dielectric layer over the third dielectric layer; and
forming a via hole through the fourth dielectric layer and the first graphene layer.

12. The method of claim 8 , further comprising:
forming a second graphene layer over the via.

13. The method of claim 12 , wherein forming the metal line comprises depositing a metal layer over the conductive layer and etching the metal layer, and wherein forming the second graphene layer is performed prior to etching the metal layer.

14. A method, comprising:
forming a via hole through a first dielectric layer to expose a conductive layer;
forming a barrier layer having a first portion to line the via hole and a second portion extending along a top surface of the first dielectric layer;
forming a metal via in the via hole and over the barrier layer;
forming a first graphene layer over the metal via and enclosed by the second portion of the barrier layer;
forming a metal layer over the first graphene layer; and
etching the metal layer to form a metal line over the first graphene layer such that the metal line is in contact with the first graphene layer and the barrier layer, wherein etching the metal layer is performed such that a sidewall of the metal line is exposed and the second portion of the barrier layer remains enclosing the first graphene layer after the etching the metal layer.

15. The method of claim 14 , wherein forming the first graphene layer is performed to cover an entirety of a top surface of the metal via.

16. The method of claim 15 , wherein the entirety of the top surface of the metal via remains covered by the first graphene layer after etching the metal layer.

17. The method of claim 14 , further comprising:
annealing the metal via prior to forming the first graphene layer.

18. The method of claim 14 , further comprising:
forming a second graphene layer that is in contact with the barrier layer.

19. The method of claim 14 , further comprising:
forming a second capping layer that peripherally encloses the first graphene layer.

20. The method of claim 14 , wherein the barrier layer is in contact with a top surface of the first dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yang Shin-Yi
• Lee Ming-Han
• Shue Shau-Lin

Classifications

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/4462

  Carbon or carbon-containing materials, e.g. graphene · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title