Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9431345-B2
Application number	US-201314022505-A
Country	US
Kind code	B2
Filing date	Sep 10, 2013
Priority date	Mar 25, 2013
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

According to one embodiment, a semiconductor device includes a metal interconnect and a graphene interconnect which are stacked to one another.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plug;
a metal interconnect;
a graphene interconnect; and
an insulation region,
wherein
the plug is formed in the insulation region, electrically connected to the metal interconnect, and has a top surface and a bottom surface parallel with each other, and side surfaces between the top surface and the bottom surface,
the metal interconnect includes a main body portion and a barrier metal portion provided on a bottom surface and side surfaces of the main body portion, a top surface of the main body portion being located lower than a top surface of the barrier metal portion,
the graphene interconnect is formed on the top surface of the main body portion, on the insulation region and on portions of the side surfaces of the plug, and
the insulation region has an inclined surface around the plug.

2. The device of claim 1 , further comprising:
a catalyst layer serving as a catalyst when the graphene interconnect is formed on the top surface of the main body portion of the metal interconnect, the catalyst layer being provided between the top surface of the main body portion of the metal interconnect and the graphene interconnect.

3. The device of claim 2 , wherein the catalyst layer includes at least one of cobalt (Co), nickel (Ni) and iron (Fe) as a principal ingredient.

4. The device of claim 1 , wherein the metal interconnect includes one of a copper (Cu) interconnect, a tungsten (W) interconnect, and an aluminum (Al) interconnect.

5. The device of claim 1 , wherein the graphene interconnect is a multilayered graphene interconnect.

Assignees

• Toshiba Kk

Inventors

• Sakata Atsuko
• Kitamura Masayuki
• Wada Makoto
• Katagiri Masayuki
• Yamazaki Yuichi
• Kajita Akihiro

Classifications

• H10W20/0372

  comprising multiple barrier, adhesion or liner layers · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title