Methods of forming graphene contacts on source/drain regions of FinFET devices

Patent metadata

Field	Value
Publication number	US-9972537-B2
Application number	US-201615052098-A
Country	US
Kind code	B2
Filing date	Feb 24, 2016
Priority date	Feb 24, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

One illustrative method disclosed herein includes forming a gate structure above a portion of a fin and performing a first epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above the fin in the source and drain regions of a FinFET device. In this example, the method also includes performing a heating process so as to form a source/drain graphene contact from the silicon-carbide (SiC) semiconductor material in both the source and drain regions of the FinFET device and forming first and second source/drain contact structures that are conductively coupled to the source/drain graphene contact in the source region and the drain region, respectively, of the FinFET device.

First claim

What is claimed:

1. A method forming a FinFET device comprised of a source region and a drain region that are positioned on opposite sides of a gate structure, comprising:
forming a fin in a semiconductor substrate comprised of a first semiconductor material;
forming said gate structure above a portion of said fin;
performing a first epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above said fin in said source and drain regions of said FinFET device, said silicon-carbide (SiC) semiconductor material being a different semiconductor material than said first semiconductor material of said substrate;
performing a heating process so as to form a source/drain graphene contact from said silicon-carbide (SiC) semiconductor material in both said source and drain regions of said FinFET device; and
forming first and second source/drain contact structures that are conductively coupled to said source/drain graphene contact in said source region and said drain region, respectively, of said FinFET device.

2. The method of claim 1 , wherein said silicon-carbide (SiC) semiconductor material comprises one of 3C—SiC, a carbon-doped silicon, a hydrogen-rich carbon-doped silicon, an amorphous silicon-carbide or a polycrystalline silicon-carbide.

3. The method of claim 1 , wherein, prior to performing said first epitaxial growth process, the method comprises performing a second epitaxial growth process to form a source/drain epi semiconductor material on said fin, wherein said source/drain epi semiconductor material is different from said first semiconductor material of said substrate and wherein performing said first epitaxial growth process comprises performing said first epitaxial growth process so as to form said silicon-carbide (SiC) semiconductor material on and in physical contact with said source/drain epi semiconductor material.

4. The method of claim 1 , wherein performing said heating process so as to form said source/drain graphene contact comprises performing said heating process at a temperature that falls within a range of about 600-800° C.

5. The method of claim 1 , wherein said fin is made entirely of said first semiconductor material.

6. The method of claim 5 , wherein performing said first epitaxial growth process comprises performing said first epitaxial growth process so as to form said silicon-carbide (SiC) semiconductor material on and in physical contact with said first semiconductor material that comprises said fin.

7. The method of claim 1 , wherein a lower portion of said fin is made of said first semiconductor material and an upper portion of said fin is made of a third semiconductor material that is different from said first semiconductor material.

8. The method of claim 7 , wherein said third semiconductor material is comprised of one of silicon germanium (Si x Ge (1-x) (where x ranges from 0.1 to about 0.9)) or at least one III-V semiconductor material.

9. The method of claim 1 , wherein forming said gate structure comprises forming a sacrificial gate structure.

10. The method of claim 1 , wherein forming said gate structure comprises forming a final gate structure for said FinFET device.

11. A method forming a FinFET device comprised of a source region and a drain region that are positioned on opposite sides of a gate structure, comprising:
forming a fin in a substrate comprised of a first semiconductor material;
forming said gate structure above a portion of said fin;
performing a first epitaxial growth process to form a source/drain epi semiconductor material on said fin, wherein said source/drain epi semiconductor material is a different semiconductor material from said first semiconductor material of said substrate;
performing a second epitaxial growth process to form a silicon-carbide (SiC) semiconductor material on and in contact with said source/drain epi semiconductor material in said source and drain regions of said FinFET device, said silicon-carbide (SiC) semiconductor material being a different semiconductor material than said first semiconductor material of said substrate;
performing a heating process so as to form, via sublimation, a source/drain graphene contact from said silicon-carbide (SiC) semiconductor material in both said source and drain regions of said FinFET device; and
forming first and second source/drain contact structures that are conductively coupled to said source/drain graphene contact in said source region and said drain region, respectively, of said FinFET device.

12. The method of claim 11 , wherein said FinFET device is a PMOS FinFET device and wherein said second semiconductor material is silicon germanium (Si x Ge (1-x) (where x ranges from 0.1 to about 0.9)) and wherein performing said second epitaxial growth process comprises performing said second epitaxial growth process so as to form said silicon-carbide (SiC) semiconductor material on and in contact with said source/drain epi semiconductor material.

13. The method of claim 11 , wherein said FinFET device is an NMOS FinFET device and wherein said second semiconductor material is silicon-carbide (SiC) and wherein performing said second epitaxial growth process comprises performing said second epitaxial growth process so as to form said silicon-carbide (SiC) semiconductor material on and in contact with said source/drain epi semiconductor material.

14. The method of claim 11 , wherein performing said heating process so as to form said source/drain graphene contact comprises performing said heating process at a temperature that falls within a range of about 600-800° C.

15. The method of claim 11 , wherein said fin is made entirely of said first semiconductor material.

16. The method of claim 11 , wherein a lower portion of said fin is made of said first semiconductor material and an upper portion of said fin is made of a third semiconductor material that is a different semiconductor material than said first semiconductor material.

17. The method of claim 16 , wherein said third semiconductor material is comprised of one of silicon germanium (Si x Ge (1-x) (where x ranges from 0.1 to about 0.9)) or at least one III-V semiconductor material.

18. A method of forming an integrated circuit product comprised of a PMOS FinFET device and an NMOS FinFET device, each of said FinFET devices comprising a source region and a drain region that are positioned on opposite sides of a gate structure, comprising:
forming first and second fins in a substrate comprised of a first semiconductor material, said first and second fins being formed for said PMOS FinFET device and said NMOS FinFET device, respectively;
forming first and second gate structures above a portion of said first and second fins, respectively;
forming a first source/drain epi second semiconductor material on said first fin in said source and drain regions of said PMOS FinFET device, wherein said first source/drain epi second semiconductor material is a different semiconductor material than said first semiconductor material of said substrate;
forming a second source/drain epi semiconductor material on said second fin in said source and drain regions of said NMOS FinFET device, wherein said second source/drain epi semiconductor material is a different semiconductor material from said first semiconductor material and said second source/drain epi semiconductor material;
forming a silicon-carbide (SiC) semiconductor material on and in contact with said first source/drain epi semiconductor material in said source and drain regions of said PMOS FinFET device and on and in contact

Assignees

• Globalfoundries Inc

Inventors

• Jacob Ajey Poovannummoottil

Classifications

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3408

  Silicon carbide · CPC title

• H10P14/3406

  Carbon, e.g. diamond-like carbon · CPC title

• H10P14/3208

  Silicon carbide · CPC title