Methods for making three-dimensional module

Patent metadata

Field	Value
Publication number	US-11616030-B2
Application number	US-202117539040-A
Country	US
Kind code	B2
Filing date	Nov 30, 2021
Priority date	Jul 10, 2019
Publication date	Mar 28, 2023
Grant date	Mar 28, 2023

Abstract

A method for making a three-dimensional (3-D) module includes the steps of: A) forming a laminate of alternate ceramic tape layers and internal electrode layers on a substrate; B) etching said laminate to form first and second capacitor stacks at said first and second locations; C) firing said first and second capacitor stacks integrally; D) forming first and second pairs of external electrodes on said first and second capacitor stacks, respectively.

First claim

What is claimed is:

1. A method for making a three-dimensional (3-D) module including first and second capacitors at first and second locations on a substrate, comprising the steps of:
A) forming a first laminate of alternate ceramic tape layers and internal electrode layers at said first and second locations on said substrate;
B) forming a second laminate of alternate ceramic tape layers and internal electrode layers on said first laminate at said first location, and forming a dummy portion comprising only ceramic tape layers on said first laminate at said second location;
C) etching said first laminate, said second laminate and said dummy portion to form first and second capacitor stacks at said first and second locations;
D) firing said first and second capacitor stacks integrally;
E) forming first and second pairs of external electrodes on said first and second capacitor stacks, respectively;
wherein said internal electrode layers carry the patterns of internal electrodes for said first and second capacitors at said first and second locations; said dummy portion at said second location does not comprise any internal electrode layers; and, said first laminate is closer to said substrate than said dummy portion.

2. The method according to claim 1 , wherein said first capacitor does not comprise any dummy portion.

3. The method according to claim 1 , wherein the thickness of said dummy portion is at least twice as much as a largest distance between adjacent ones of said internal electrodes in said second capacitor.

4. The method according to claim 1 , wherein each internal electrode of said second capacitor is co-planar with a selected one of the internal electrodes of said first capacitor.

5. The method according to claim 1 , further comprising a structural material surrounding and physically contacting the side surfaces of said first and second capacitors, wherein said structural material mechanically interconnects in a spaced, planar relation said first and second capacitors.

6. A method for making a three-dimensional (3-D) module including first and second capacitors at first and second locations on a substrate, comprising the steps of:
A) forming a first laminate of alternate ceramic tape layers and internal electrode layers at said first and second locations on said substrate;
B) forming a second laminate of alternate ceramic tape layers and internal electrode layers on said first laminate at said first location, and forming a dummy portion comprising only ceramic tape layers on said first laminate at said second location;
C) forming a third laminate of alternate ceramic tape layers and internal electrode layers at said first and second locations on said second laminate and said dummy portion;
D) etching said first laminate, said second laminate, said dummy portion and said third laminate to form first and second capacitor stacks at said first and second locations;
E) firing said first and second capacitor stacks integrally;
F) forming first and second pairs of external electrodes on said first and second capacitor stacks, respectively;
wherein said internal electrode layers carry the patterns of internal electrodes for said first and second capacitors at said first and second locations; said dummy portion at said second location does not comprise any internal electrode layers; said first laminate is closer to said substrate than said dummy portion; and, said dummy portion is closer to said substrate than said third laminate.

7. The method according to claim 6 , wherein said first capacitor does not comprise any dummy portion.

8. The method according to claim 6 , wherein the thickness of said dummy portion is at least twice as much as a largest distance between adjacent ones of said internal electrodes in said second capacitor.

9. The method according to claim 6 , wherein each internal electrode of said second capacitor is co-planar with a selected one of the internal electrodes of said first capacitor.

10. The method according to claim 6 , further comprising a structural material surrounding and physically contacting the side surfaces of said first and second capacitors, wherein said structural material mechanically interconnects in a spaced, planar relation said first and second capacitors.

Assignees

• Univ Southern Sci & Tech

Inventors

• Zhang Guobiao
• Yu Hongyu
• Zhou Shengming
• Guo Yuejin
• Chen Kai
• Li Yida
• Lan Jun

Classifications

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title